Commit 674df99c authored by Stefan Tauner's avatar Stefan Tauner
Browse files

netlist.pm: output quotes around all HDL identifiers to ease debugging of escaped identifiers

parent 0488cca2
......@@ -224,12 +224,12 @@ sub _check_name_in_hierarchy {
my ($startmod, $name) = @_;
my $nl = $startmod->netlist;
$logger->debug("Checking " . $startmod->name . " for name $name");
$logger->debug("Checking \"" . $startmod->name . "\" for name \"$name\"");
# check if a net is named the same
for my $net ($startmod->nets) {
if ($net->name eq $name) {
my $msg = "Name $name does already exist as net in " . $startmod->name;
my $msg = "Name \"$name\" does already exist as net in " . $startmod->name;
return $msg;
}
}
......@@ -237,14 +237,14 @@ sub _check_name_in_hierarchy {
# check if a port is named the same
for my $port ($startmod->ports) {
if ($port->name eq $name) {
my $msg = "Name $name does already exist as port in " . $startmod->name;
my $msg = "Name \"$name\" does already exist as port in " . $startmod->name;
return $msg;
}
}
for my $cell ($startmod->cells) {
if ($cell->name eq $name) {
my $msg = "Name $name does already exist as cell in " . $startmod->name;
my $msg = "Name \"$name\" does already exist as cell in " . $startmod->name;
return $msg;
}
}
......@@ -287,7 +287,7 @@ sub _add_port_to_hierarchy {
return undef if ($startmod->find_port($name));
$logger->debug($indent . "Adding port $name to module " . $startmod->name);
$logger->debug($indent . "Adding port \"$name\" to module \"" . $startmod->name . "\"");
# decide direction
if ( $function == FIJI::VHDL->FIJI_PORTTYPE_MODIFIED
......@@ -320,8 +320,8 @@ sub _add_port_to_hierarchy {
foreach my $mod ($nl->modules_sorted) {
foreach my $cell ($mod->cells) {
if (defined $cell->submod && $cell->submod == $startmod) {
$logger->debug($indent . "Adding pin $name to cell " . $cell->name);
$logger->debug($indent . "Connecting pin " . $cell->name . HIERSEP . $name . " to port " . $np->module->name . HIERSEP . $np->name);
$logger->debug($indent . "Adding pin \"$name\" to cell \"" . $cell->name . "\"");
$logger->debug($indent . "Connecting pin \"" . $cell->name . HIERSEP . $name . "\" to port \"" . $np->module->name . HIERSEP . $np->name . "\"");
$cell->new_pin(
name => $name,
portname => $np->name,
......@@ -358,7 +358,7 @@ sub net_add_function {
my $logger = get_logger("");
my ($self, $net, $function, $port_name, $index) = @_;
$logger->debug("Adding function to " . $net->module->name . ", net " . $net->name);
$logger->debug("Adding function to \"" . $net->module->name . "\", net \"" . $net->name . "\"");
my $prefix = "fiji_";
while (1) {
......@@ -371,10 +371,10 @@ sub net_add_function {
}
}
$logger->debug($port_name . " can be used as fiji connector");
$logger->debug("\"" . $port_name . "\" can be used as fiji connector");
my $op = _add_port_to_hierarchy($net->module, $port_name, $function, $index);
$logger->debug("Connecting Port " . $op->name . " to net " . $net->name);
$logger->debug("Connecting Port \"" . $op->name . "\" to net \"" . $net->name . "\"");
# connect the net to the newly created port
$net->module->new_contassign(
......@@ -398,8 +398,8 @@ sub net_add_function {
#
# @param net the Verilog::Net to instrument
# @param fiu_idx the FIU number this external access shall be connected to
# @param driver_path the path to the driver of this net (optional)
# @param driver_type the type of the driver (can be PIN, PORT, ASSIGN)
# @param driver_path the path to the driver of this net (optional but depends on driver_type)
# @param driver_type the type of the driver (can be PIN, PORT, ASSIGN) (optional but depends on driver_path)
#
# @returns STRING if an error occurred
# @returns undef if successful
......@@ -456,13 +456,13 @@ sub instrument_net {
$msg = _check_name_in_hierarchy($net->module, $output_name);
return $msg if defined $msg;
$logger->debug($output_name . " will be used as fiji connector (output)");
$logger->debug("\"" . $output_name . "\" will be used as fiji connector (output)");
my $op = _add_port_to_hierarchy($net->module, $output_name, FIJI::VHDL->FIJI_PORTTYPE_ORIGINAL, $fiu_idx);
$msg = _check_name_in_hierarchy($net->module, $input_name);
return $msg if defined $msg;
$logger->debug($input_name . " will be used as fiji connector (input)");
$logger->debug("\"" . $input_name . "\" will be used as fiji connector (input)");
my $ip = _add_port_to_hierarchy($net->module, $input_name, FIJI::VHDL->FIJI_PORTTYPE_MODIFIED, $fiu_idx);
my %connections;
......@@ -475,7 +475,7 @@ sub instrument_net {
if (ref($connection) eq "Verilog::Netlist::Pin") {
# if it is a pin of a cell, connect this pin to the newly created net
$log .= "(output) pin " . $connection->cell->name . HIERSEP . $connection->name;
$log .= "(output) pin \"" . $connection->cell->name . HIERSEP . $connection->name . "\"";
for my $netname (@{$connection->netnames}) {
# @FIXME work to be done for Buses
......@@ -496,7 +496,7 @@ sub instrument_net {
# @FIXME work to be done for Buses
# if it is a port of a module, connect this port to the newly created net
$log .= "(input) port " . $connection->name;
$log .= "(input) port \"" . $connection->name . "\"";
$connection->net($op->net);
$net->module->new_contassign(
keyword => "assign",
......@@ -507,10 +507,10 @@ sub instrument_net {
);
} elsif (ref($connection) eq "Verilog::Netlist::ContAssign") {
# @FIXME work to be done for Buses
$log .= "assignment " . $connection->lhs;
$log .= "assignment of \"" . $connection->lhs . "\"";
$connection->rhs($connection->rhs =~ s/^\Q$net->name\E$/oip->net->name/r);
}
$log .= " to generated output " . $op->name;
$log .= " to generated output \"" . $op->name . "\"";
$logger->debug($log);
# create interconnections for newly created port/pin
......@@ -523,7 +523,7 @@ sub instrument_net {
foreach my $connection (@{$connections{'driven'}}) {
my $log = "Modified: Connecting ";
if (ref($connection) eq "Verilog::Netlist::Pin") {
$log .= "(input) pin " . $connection->cell->name . HIERSEP . $connection->name;
$log .= "(input) pin \"" . $connection->cell->name . HIERSEP . $connection->name . "\"";
for my $netname (@{$connection->netnames}) {
# @FIXME work to be done for Buses
......@@ -541,7 +541,7 @@ sub instrument_net {
$connection->port(undef); # resolved by link
} elsif (ref($connection) eq "Verilog::Netlist::Port") {
# @FIXME work to be done for Buses
$log .= "(output) port " . $connection->module->name . HIERSEP . $connection->name;
$log .= "(output) port \"" . $connection->module->name . HIERSEP . $connection->name . "\"";
$net->module->new_contassign(
keyword => "assign",
lhs => $connection->name.$idx,
......@@ -551,10 +551,10 @@ sub instrument_net {
);
} elsif (ref($connection) eq "Verilog::Netlist::ContAssign") {
# @FIXME work to be done for Buses
$log .= "assignment " . $connection->rhs;
$log .= "assignment of \"" . $connection->rhs . "\"";
$connection->lhs($connection->lhs =~ s/\Q$net->name\E)?$/$ip->net->name/r);
}
$log .= " to generated input " . $ip->name;
$log .= " to generated input \"" . $ip->name . "\"";
$logger->debug($log);
# create interconnections for newly created port/pin
......@@ -690,7 +690,7 @@ sub get_connection_object {
if ($connection_type eq "PIN") {
if ($connection_path =~ /^(.+)\Q$SEP\E(.+)\Q$SEP\E(.+)$/) {
$logger->debug("Looking for pin named $3 in cell $2 of module $1...");
$logger->debug("Looking for pin named \"$3\" in cell \"$2\" of module \"$1\"...");
my $mod = $self->{'nl'}->find_module($1);
my $cell = $mod->find_cell($2) if (defined $mod);
......@@ -700,7 +700,7 @@ sub get_connection_object {
} elsif ($connection_type eq "PORT") {
if ($connection_path =~ /^(.+)\Q$SEP\E(.+)$/) {
$logger->debug("Looking for port named $2 in module $1...");
$logger->debug("Looking for port named \"$2\" in module \"$1\"...");
my $mod = $self->{'nl'}->find_module($1);
my $port = $mod->find_port($2) if (defined $mod);
......@@ -710,7 +710,7 @@ sub get_connection_object {
if ($connection_path =~ /^(.+)\Q$SEP\E(.+)$/) {
my $lhs = $2;
$logger->debug("Looking for assignment to/from $2 in module $1...");
$logger->debug("Looking for assignment to/from \"$2\" in module \"$1\"...");
my $mod = $self->{'nl'}->find_module($1);
if (defined $mod) {
......@@ -718,7 +718,7 @@ sub get_connection_object {
for my $a (grep { $_->isa("Verilog::Netlist::ContAssign") } $mod->statements) {
if ($a->lhs eq $lhs || $a->rhs =~ /\Q$lhs\E/) {
$assign = $a;
$logger->debug("Constant assignment: $assign");
$logger->debug(sprintf("Constant assignment: \"%s\" = \"%s\"", $a->lhs, $a->rhs));
last;
}
}
......@@ -766,9 +766,8 @@ sub _get_net_connections_from_path {
# connection_hashref->{'driven'} contains a list of driven cells
# connection_hashref->{'connected'} contains a list cells connected to the
# net but driver/driven cannot be decided
# @param driver (optional) preselected driver of the net
# is a hash consisting of 'driver_path' and
# 'driver_type'
# @param driver_path the path to the driver of this net (optional but depends on driver_type)
# @param driver_type the type of the driver (can be PIN, PORT, ASSIGN) (optional but depends on driver_path)
sub _get_net_connections {
my $logger = get_logger("");
my ($self, $net, $connection_hashref, $driver_path, $driver_type) = @_;
......@@ -815,16 +814,16 @@ sub _get_net_connections {
my $mod = $net->module;
$logger->debug("Net ".$mod->name.HIERSEP.$net->name.", connections:");
$logger->debug("Net \"" . $mod->name . HIERSEP . $net->name . "\", connections:");
# find nets driven by continuous assignment (e.g., constant or inverter)
foreach my $statement ($mod->statements) {
if ($statement->lhs eq $net->name) {
# continuous assign statement to this net, there can't be another driver
# FIXME: use that knowledge to fail early (if another iteration matches too)?
$logger->debug(" assign: " . $mod->name . ": " . $net->name . " = " . $statement->rhs);
# FIXME: use that knowledge to fail early (if another iteration or loop matches too)?
$logger->debug(" assign: \"" . $mod->name . "\": \"" . $net->name . "\" = \"" . $statement->rhs . "\"");
if (defined $driver && $assign_driver_supplied && $statement != $driver) {
return "Driver mismatch: ".($statement->rhs)." is not $driver_path";
return "Driver mismatch: actual \"" . ($statement->rhs) . "\" is not given \"$driver_path\"";
}
push @drivers, $statement;
} elsif ($statement->rhs =~ /\Q$net->name\E$/) {
......@@ -835,26 +834,30 @@ sub _get_net_connections {
# find nets driven by this module's input ports
foreach my $port ($mod->ports) {
if (defined $port->net && ($port->net->name eq $net->name)) {
$logger->debug(" port: " . $mod->name . HIERSEP . $port->name);
$logger->debug(" port: \"" . $mod->name . HIERSEP . $port->name . "\"");
# driven from an input, there can't be another driver
if ($port->direction eq "in") {
# driven from an input, there can't be another driver
# FIXME: use that knowledge to fail early (if another loop matches too)?
if (defined $driver && $port_driver_supplied && $port != $driver) {
return "Driver mismatch: $port->name is not $driver_path";
return "Driver mismatch: actual driver \"$port->name\" is not given \"$driver_path\"";
}
push @drivers, $port;
} elsif ($port->direction eq "out") {
push @driven, $port;
} elsif ($port->direction eq "inout") {
if (!defined $driver) {
push @connected, $port;
# inout might be the driver but we can't be sure without a preselection.
# However, we can note that it is connected for sure.
if (!defined $driver) {
push @connected, $port;
} else {
# If the preselected driver matches this port we note it as the driver
if (!$assign_driver_supplied && !$pin_driver_supplied && ($port == $driver)) {
push @drivers, $port;
} else {
if (!$assign_driver_supplied && !$pin_driver_supplied && ($port == $driver)) {
push @drivers, $port;
} else {
push @driven, $port;
}
push @driven, $port;
}
}
}
}
}
......@@ -862,18 +865,21 @@ sub _get_net_connections {
# find nets driven by other cells' output pins
foreach my $cell ($mod->cells) {
foreach my $pin ($cell->pins) {
# skip all input pins of the contained cells - it can't drive "us"
next if defined($pin->port) && $pin->port->direction eq 'in';
foreach my $netname (@{$pin->netnames}) {
if ($netname->{'netname'} eq $net->name) {
if (!_is_pinrange_in_net($net->msb, $net->lsb, $net)) {
$logger->warn("Out of range (of net ${net->name})\n");
$logger->warn("Out of range (of net \"${net->name}\")\n");
next;
}
$logger->debug(" pin " . $pin->cell->name . HIERSEP . $pin->name);
$logger->debug(" pin \"" . $pin->cell->name . HIERSEP . $pin->name . "\"");
# The pin might be the driver but we can't be sure without a preselection.
# However, we can note that it is connected for sure.
if (!defined $driver) {
push @connected, $pin;
} else {
# If the preselected driver matches this pin we note it as the driver
if (!$assign_driver_supplied && !$port_driver_supplied && $pin_driver_supplied && ($pin == $driver)) {
push @drivers, $pin;
} else {
......@@ -917,7 +923,7 @@ sub export {
print $fh_nl "//------------------------------------------------------------------------------\n\n";
for my $mod ($self->{'nl'}->modules) {
$logger->debug("Exporting module " . $mod->name);
$logger->debug("Exporting module \"" . $mod->name . "\"");
my $verilog_text = $mod->verilog_text;
print $fh_nl $verilog_text;
}
......
......@@ -37,7 +37,10 @@ sub Populate {
sub Show {
my ($self) = @_;
if (defined $self->{'mw'} && defined $self->{'delete_mw'}) {
$self->{'mw'}->protocol('WM_DELETE_WINDOW' => sub {return 1});
$self->{'mw'}->protocol('WM_DELETE_WINDOW' => sub {
$self->{'mw'}->destroy(); # according to Mastering O'Reilly
return 1;
});
}
my $rv = $self->SUPER::Show();
if (defined $self->{'mw'} && defined $self->{'delete_mw'}) {
......
......@@ -1256,7 +1256,6 @@ sub _validate_net_entry {
if (defined($widget->{'dependents'})) {
foreach my $w (@{$widget->{'dependents'}}) {
if ($w->isa("Tk::Entry")) {
$logger->debug("$w isa Tk::Entry");
if (!$ok) {
${$w->cget('-textvariable')} = "";
_highlight_widget($w, 1);
......
......@@ -81,8 +81,8 @@ wire VCC;
lut cell1 (.a(bus_i[0]), .b(bus_i[1]), .c(net_i), .d(net_i_n), .y(cell1_o_y));
lut cell2 (.a(cell1_o_y), .b(net_i_n), .c(\dumb.non.hierarchical_bus [0]), .d(\dumb.non.hierarchical_bus [1]), .y(\dumb.non.hierarchical_net ));
busmux4 cell3 (.in1(bus_i), .in2({bus1_i[3:0]}), .sel(\cell1_o_y ), .o(wirebus));
inv4 \**super_cell (.in(\dumb.non.hierarchical_bus ),.c(\cell1_o_y ),.out(bus_o));
inv4 cell5 (.in(wirebus),.c(\dumb.non.hierarchical_net ), .out(bus1_o));
inv4 \**super_cell (.in(\dumb.non.hierarchical_bus ), .c(\cell1_o_y ), .out(bus_o));
inv4 cell5 (.in(wirebus), .c(\dumb.non.hierarchical_net ), .out(bus1_o));
dff dff1 (.d(\dumb.non.hierarchical_net ), .q(oo_o), .rst(reset_i), .clk(clock_i));
......
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