Fix some minor random bugs, introduce some new ones in the netlist handling

FIJI/Downloader.pm

@@ -249,7 +249,7 @@ sub download_random ($$$;$) {
     do {
         my $temp_test = $self->{'fiji_tests'}->make_random_test( $self->{'fiji_settings'} );
         return $temp_test if ( !ref($temp_test) );
-        @tests[$ti] = $temp_test;
+        $tests[$ti] = $temp_test;
         $logger->info("=== Test $ti ===");
         $recv_msg = $self->_download_test( $tests[ $ti++ ], $port );
         return "UART transaction failed." if ( ref($recv_msg) ne "HASH" );

FIJI/Netlist.pm

@@ -333,16 +333,25 @@ sub net_add_function ($$$;$) {
 # params
 #   net the Verilog::Net to instrument
 #   fiu_idx the FIU number this external access shall be connected to
-#   driver the driver of this net (can be pin, port or contassign) (optional)
-sub instrument_net ($$;$) {
+#   driver the driver of this net (optional)
+#   driver_type the type of the driver (can be PIN, PORT, ASSIGN)
+sub instrument_net ($$;$$) {
 
     #FIXME only works with single-bit pins/ports/nets
     my $logger = get_logger("");
-    my ( $self, $net, $fiu_idx, $driver ) = @_;
+    my ( $self, $net, $fiu_idx, $driver, $driver_type ) = @_;
     my $msg;
 
     $logger->info( "Instrumenting " . $net->module->name . ", net " . $net->name );
 
+    # 1. Try to find a suitable driver.
+    #   - Get all candidates from _get_net_connections()
+    #     (this includes identified drivers as well as candidates)
+    #   - If we can't identify any drivers then rely on the parameter, or
+    #     if that is undefined we ask the user here (FIXME: this seems like a candidate for refactoring)
+    #     To that end, modify the connections hash accordingly.
+    #   - If a single driver is found then we make sure it matches the parameter (if available)
+    #   - If no or mulitple drivers are found eventually we abort.
     my %connections;
     $self->_get_net_connections( $net, \%connections );
 
@@ -600,7 +609,7 @@ sub get_connection_object($$) {
                     }
                 }
             }
-            $rv = $a;
+            $rv = $assign;
         }
     }
     return $rv;
@@ -627,7 +636,6 @@ sub _get_net_connections ($$) {
     my @drivers     = ();
     my @driven      = ();
     my @connected   = ();
-    my $debug       = 0;
 
     # FIXME what to do with bussed nets
     # FIXME what to do with instantiations like that (concatenated nets):
@@ -641,63 +649,45 @@ sub _get_net_connections ($$) {
     #
     # TODO: can Verilog::Language::split_bus help us here?
 
-    my @netnames_list = ();
+    # if ( $netname =~ m/.+\[([0-9]+)\]/ ) {
+        # my $idx = $1;
+    # }
+    $logger->debug( "Net " . $mod->name . $HIERSEP . $net->name . ", connections:" );
 
-    # This generates a list of net names for buses e.g.
-    # wire [3:0] bus
-    #   netnames = (bus[0],bus[1],bus[2],bus[3])
-    # FIXME there must be a cleaner alternative
-    if ( ( defined $net->msb && defined $net->lsb ) ) {
-        for ( my $i = $net->lsb ; $i <= $net->msb ; $i++ ) {
-            push @netnames_list, $net->name . "[$i]";
-        }
-    } else {
-        push @netnames_list, $net->name;
-    }
-
-    # check each netname
-    foreach my $netname (@netnames_list) {
+    # find nets driven by continuous assignment (e.g., constant or inverter)
+    foreach my $statement ( $mod->statements ) {
+        if ( $statement->lhs eq $net->name ) {
 
-        if ( $netname =~ m/.+\[([0-9]+)\]/ ) {
-            my $idx = $1;
+            # continuous assign statement to this net, there can't be another driver
+            $logger->debug( "    assign: " . $mod->name . ": " . $net->name . " = " . $statement->rhs );
+            push @drivers, $statement;
+        } elsif ( $statement->rhs =~ /\Q$net->name\E$/ ) {
+            push @driven, $statement;
         }
-        my $bn = $net->name;
-
-        $logger->debug( "Net " . $mod->name . $HIERSEP . $netname . ", connections:" );
-
-        # find nets driven by continuous assignment (e.g., constant or inverter)
-        foreach my $statement ( $mod->statements ) {
-            if ( $statement->lhs eq $netname ) {
+    }
 
-                # continuous assign statement to this net, there can't be another driver
-                $logger->debug( "    assign: " . $mod->name . ": " . $netname . " = " . $statement->rhs );
-                push @drivers, $statement;
-            } elsif ( $statement->rhs =~ /\Q$netname\E$/ ) {
-                push @driven, $statement;
-            }
-        }
+    # find nets driven by this module's input ports
+    foreach my $port ( $mod->ports_sorted ) {
+        if ( defined $port->net && ( $port->net->name eq $net->name ) ) {
+            $logger->debug( "    port:   " . $mod->name . $HIERSEP . $port->name );
 
-        # find nets driven by this module's input ports
-        foreach my $port ( $mod->ports_sorted ) {
-            if ( defined $port->net && ( $port->net->name eq $netname ) ) {
-                $logger->debug( "    port:   " . $mod->name . $HIERSEP . $port->name );
-
-                # driven from an input, there can't be another driver
-                if ( $port->direction eq "in" ) {
-                    push @drivers, $port;
-                } elsif ( $port->direction eq "out" ) {
-                    push @driven, $port;
-                } elsif ( $port->direction eq "inout" ) {
-                    push @connected, $port;
-                }
+            # driven from an input, there can't be another driver
+            if ( $port->direction eq "in" ) {
+                push @drivers, $port;
+            } elsif ( $port->direction eq "out" ) {
+                push @driven, $port;
+            } elsif ( $port->direction eq "inout" ) {
+                push @connected, $port;
             }
         }
+    }
 
-        # find nets driven by other cells output pins
-        foreach my $cell ( $mod->cells_sorted ) {
-            foreach my $pin ( $cell->pins_sorted ) {
-                if ( $pin->netname eq $netname ) {
-                    $logger->debug( "    pin " . $pin->cell->name . $HIERSEP . $pin->name );
+    # find nets driven by other cells output pins
+    foreach my $cell ( $mod->cells_sorted ) {
+        foreach my $pin ( $cell->pins_sorted ) {
+            foreach my $netname (@{$pin->netnames}) {
+                if ( $netname eq $net->name ) {
+                    $logger->debug( "    pin " . $pin->cell->name . $HIERSEP . $netname );
                     push @connected, $pin;
                 }
             }

FIJI/Settings.pm

@@ -666,7 +666,7 @@ sub _est_resources {
     $logger->debug("TIMER_WIDTH $TIMER_WIDTH out of range (1 - 8)")           if ( $TIMER_WIDTH < 1     || $TIMER_WIDTH > 8 );
     $logger->debug("RESET_CYCLES $RESET_CYCLES out of range (1 - 16)")        if ( $RESET_CYCLES < 1    || $RESET_CYCLES > 16 );
     $logger->debug("LFSR_WIDTH $LFSR_WIDTH out of range (16 - 64)")           if ( $LFSR_WIDTH < 16     || $LFSR_WIDTH > 64 );
-    $logger->debug("FIU_NUM $FIU_NUM out of range (0 - 64)")                  if ( $FIU_NUM < 1         || $FIU_NUM > 64 );
+    $logger->debug("FIU_NUM $FIU_NUM out of range (1 - 64)")                  if ( $FIU_NUM < 1         || $FIU_NUM > 64 );
 
     if ( $algo eq "logarithmic" ) {
         $registers = 105.90215234;