Commit 65c2fd41 authored by Stefan Tauner's avatar Stefan Tauner
Browse files

docs: fix some minor phrasing and formatting problems

parent 3793a17f
...@@ -196,7 +196,7 @@ It gets its commands from the \texttt{Tk}/main thread via a \texttt{Thread::Queu ...@@ -196,7 +196,7 @@ It gets its commands from the \texttt{Tk}/main thread via a \texttt{Thread::Queu
In the following section the contents of the \texttt{test} directory are described. In the following section the contents of the \texttt{test} directory are described.
\subsection{\ac{FIC} Emulator} \subsubsection{\ac{FIC} Emulator}
\label{sec:fic_emulator} \label{sec:fic_emulator}
The \ac{FIC} emulator is intended for testing/debugging the \ac{FIJIEE} scripts. The \ac{FIC} emulator is intended for testing/debugging the \ac{FIJIEE} scripts.
...@@ -263,11 +263,11 @@ CRC error flags can be seen. The configuration can be changed by pressing ...@@ -263,11 +263,11 @@ CRC error flags can be seen. The configuration can be changed by pressing
any of the keys shown above the status line. The terminal to which the any of the keys shown above the status line. The terminal to which the
emulator is connected is shown at the top. emulator is connected is shown at the top.
\subsection{Instrumentation Tests} \subsubsection{Instrumentation Tests}
\label{sec:instrumentation_tests} \label{sec:instrumentation_tests}
To test our Verilog-Perl changes as well as the instrumentation code (cf.\ \Cref{sec:instrumentation}) we have set up unit tests in \texttt{test/instrument\_test} consisting of minimal netlists (in \texttt{netlists}) and associated \ac{FIJI} Settings (in \texttt{fiji}). To test our Verilog-Perl changes as well as the instrumentation code (cf.\ \Cref{sec:instrumentation}) we have set up unit tests in \texttt{test/instrument\_test} consisting of minimal netlists (in \texttt{netlists}) and associated \ac{FIJI} Settings (in \texttt{fiji}).
These tests cover many different combinations of instrumentation targets and drivers and have found many bugs in corner cases. These tests cover many different combinations of instrumentation targets and drivers, which helped to find many bugs in corner cases.
The provided Makefile will execute all \textit{mandatory} test cases, by default in 16 parallel threads. The provided Makefile will execute all \textit{mandatory} test cases, by default in 16 parallel threads.
There are also some optional test cases for Verilog features that have not been observed yet in simple netlists and hence have not been implemented (yet). There are also some optional test cases for Verilog features that have not been observed yet in simple netlists and hence have not been implemented (yet).
...@@ -276,8 +276,8 @@ The unit tests consist of the following phases. ...@@ -276,8 +276,8 @@ The unit tests consist of the following phases.
\item[Setup] If there exists no \ac{FIJI} Settings file for a respective netlist \texttt{fiji\_setup.pl} will be launched to allow the engineer to choose the instrumented net(s) and possibly set other settings needed for the test. \item[Setup] If there exists no \ac{FIJI} Settings file for a respective netlist \texttt{fiji\_setup.pl} will be launched to allow the engineer to choose the instrumented net(s) and possibly set other settings needed for the test.
If the Settings exist already but are older than the netlist we force make to skip launching the GUI for usability reasons. If the Settings exist already but are older than the netlist we force make to skip launching the GUI for usability reasons.
\item[Instrumentation] The netlists are instrumented with \texttt{fiji\_instrument.pl}. \item[Instrumentation] The netlists are instrumented with \texttt{fiji\_instrument.pl}.
\item[Synthesis] The instrumented netlists are quickly checked for syntax errors and the like by letting Symplify synthesize and filtering unrelated warnings. \item[Synthesis] The instrumented netlists are quickly checked for syntax errors and the like by synthesizing them with Synplify and filtering out unrelated warnings.
\item[Simulation] Additionally to the syntax check a behavioral simulation tries to find discrepancies between an instrumented and untouched entity of the respective netlist. \item[Simulation] In addition to the syntax check a behavioral simulation tries to find discrepancies between an instrumented and untouched entity of the respective netlist.
To that end the test instantiates them in a testbench and compares their output when fed some generated input. To that end the test instantiates them in a testbench and compares their output when fed some generated input.
The tests are not exhaustive but very effective since instrumentation bugs usually affect the signal path in a very direct manner. The tests are not exhaustive but very effective since instrumentation bugs usually affect the signal path in a very direct manner.
\end{description} \end{description}
\ No newline at end of file
...@@ -436,7 +436,7 @@ following entries: ...@@ -436,7 +436,7 @@ following entries:
test run to VHDL-2008 and System Verilog templates for \ac{RTL} simulation. test run to VHDL-2008 and System Verilog templates for \ac{RTL} simulation.
This HDL description contains (1) fault injection logic templates This HDL description contains (1) fault injection logic templates
which have to be integrated into the various \ac{RTL} modules manually, which have to be integrated into the various \ac{RTL} modules manually,
and (2) a scheduling process which controls these templates using and (2) a scheduling process that controls these templates using
hierarchical identifiers whose path also has to be adapted. hierarchical identifiers whose path also has to be adapted.
\item \textit{As VHDL architecture for gate-level simulation}: This \item \textit{As VHDL architecture for gate-level simulation}: This
generates a simulation-only architecture for the top-level generates a simulation-only architecture for the top-level
...@@ -456,7 +456,7 @@ As mentioned above, \ac{FIJI} helps with re-executing a test that ran in actual ...@@ -456,7 +456,7 @@ As mentioned above, \ac{FIJI} helps with re-executing a test that ran in actual
hardware as a gate-level simulation. To that end, \textit{\ac{FIJIEE}} tools hardware as a gate-level simulation. To that end, \textit{\ac{FIJIEE}} tools
are able to export the executed tests as a VHDL architecture for the top-level are able to export the executed tests as a VHDL architecture for the top-level
entity of the fault injection logic. This architecture replaces the \ac{FIC} and entity of the fault injection logic. This architecture replaces the \ac{FIC} and
the \acp{FIU} with a simulation-only description which sets the modified the \acp{FIU} with a simulation-only description that sets the modified
net outputs according to the timing of the test run previously executed in net outputs according to the timing of the test run previously executed in
hardware. hardware.
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment