Commit 62f5a1e5 authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

Assignments are now specified by LHS and RHS

parent 9cd63b4e
......@@ -45,10 +45,11 @@ use Data::Dumper;
use FIJI::VHDL;
use constant HIERSEP => "/";
use constant FIJI_NAMESPACE_PREFIX => "fiji_";
use constant EQUALSEP => "=";
use constant FIJI_NAMESPACE_PREFIX => "fiji_";
use constant FIJI_PORT_IN_POSTFIX => "_inj_i";
use constant FIJI_PORT_OUT_POSTFIX => "_ori_o";
use constant MAX_UNIQUE_TRIES => 10;
use constant MAX_UNIQUE_TRIES => 10;
use constant FIJI_LOGO => <<logo_end;
// FIJIFIJIFIJIFIJIFIJIFIJIFIJIFIJIFIJIFIJI
......@@ -611,7 +612,11 @@ sub instrument_net {
$driver_bit = $connection->userdata->{'fiji_driver_bit'};
}
$logger->debug("Connecting to intermediate net \"" . $net_name_tmp . "\" the continuous assignment of \"" . $connection->rhs . "\"");
# need to remember what was originally connected to this assign
# to instrument two nets driven by one assign
$connection->userdata('former_assign' => {'lhs' => $connection->lhs, 'rhs' => $connection->rhs});
$connection->lhs($net_name_tmp);
} else {
$logger->error("Driver instance is neither pin, port nor contassign?");
}
......@@ -800,9 +805,9 @@ sub _connection_tostr {
$type = "PORT";
$str = $type . ": " . $path
} elsif (ref($connection) eq "Verilog::Netlist::ContAssign") {
$path = $connection->module->name . HIERSEP . $connection->rhs;
$path = $connection->module->name . HIERSEP . $connection->lhs . EQUALSEP . $connection->rhs;
$type = "ASSIGN";
$str = $type . ": " . $connection->rhs;
$str = $type . ": " . $connection->lhs . EQUALSEP . $connection->rhs;
}
push @{$conn_str_list_ref}, {path => $path, type => $type} if defined $conn_str_list_ref;
return $str
......@@ -825,38 +830,46 @@ sub get_connection_object {
my $rv;
my $SEP = HIERSEP;
my @path_elements = _split_path($connection_path);
if ($connection_type eq "PIN") {
if ($connection_path =~ /^(.+)\Q$SEP\E(.+)\Q$SEP\E(.+)$/) {
if (@path_elements == 3) {
my ($module_name, $cell_name, $pin_name) = @path_elements;
$logger->trace("Looking for pin named \"$3\" in cell \"$2\" of module \"$1\"...");
$logger->trace("Looking for pin named \"$pin_name\" in cell \"$cell_name\" of module \"$module_name\"...");
my $mod = $self->{'nl'}->find_module($1);
my $cell = $mod->find_cell($2) if (defined $mod);
my $pin = $cell->find_pin($3) if (defined $cell);
my $mod = $self->{'nl'}->find_module($module_name);
my $cell = $mod->find_cell($cell_name) if (defined $mod);
my $pin = $cell->find_pin($pin_name) if (defined $cell);
$rv = $pin;
}
} elsif ($connection_type eq "PORT") {
if ($connection_path =~ /^(.+)\Q$SEP\E(.+)$/) {
if (@path_elements == 2) {
$logger->trace("Looking for port named \"$2\" in module \"$1\"...");
my ($module_name, $port_name) = @path_elements;
my $mod = $self->{'nl'}->find_module($1);
my $port = $mod->find_port($2) if (defined $mod);
$logger->trace("Looking for port named \"$port_name\" in module \"$module_name\"...");
my $mod = $self->{'nl'}->find_module($module_name);
my $port = $mod->find_port($port_name) if (defined $mod);
$rv = $port;
}
} elsif ($connection_type eq "ASSIGN") {
if ($connection_path =~ /^(.+)\Q$SEP\E(.+)$/) {
my $net = $2;
if (@path_elements >= 2) {
my $module_name = $path_elements[0];
my $assign_string = substr $connection_path, length($module_name)+1;
$logger->trace("Looking for assignment to/from \"$net\" in module \"$1\"...");
my $mod = $self->{'nl'}->find_module($1);
$logger->trace("Looking for assignment $assign_string in module \"$module_name\"...");
my $mod = $self->{'nl'}->find_module($module_name);
if (defined $mod) {
my $assign;
for my $a (grep { $_->isa("Verilog::Netlist::ContAssign") } $mod->statements) {
if ($a->lhs =~ /\Q$net\E/ || $a->rhs =~ /\Q$net\E/) {
my $former_assign = $a->userdata('former_assign');
if ($assign_string eq $a->lhs.EQUALSEP.$a->rhs || (defined $former_assign && ($former_assign->{'lhs'}).EQUALSEP.($former_assign->{'rhs'}) eq $assign_string)) {
$assign = $a;
$logger->trace(sprintf("Constant assignment: \"%s\" = \"%s\"", $a->lhs, $a->rhs));
$logger->trace(sprintf("Continuous assignment: \"%s\" = \"%s\"", $a->lhs, $a->rhs));
last;
}
}
......@@ -1020,6 +1033,8 @@ sub _get_net_connections {
foreach my $statement ($mod->statements) {
# Possibly inverted possibly vectored net possibly within a concatenation on RHS and LHS
$logger->trace("looking at \"" . $statement->lhs . "\" = \"" . $statement->rhs . "\"");
# FIXME also check for former_assign here?
# RHS. If we find our net here the statement is driven by it.
$self->_handle_connection_statement($net, $bit, \@driven, $statement, $statement->rhs);
......@@ -1169,28 +1184,13 @@ sub _offset_of_bit_in_range {
return $bit - min($range_msb, $range_lsb);
}
## @method private _extract_netpath_elements($netpath)
# @brief extracts the module name and net name from a given net path.
#
# @param netpath the hierarchical PATH|TO|netname; separator according to constant HIERSEP
# @param netpath_elements (optional) a hashref to store found elements into
#
# @returns STRING if an error occurred
# @returns HASHREF with the keys 'mod_name', 'net_string' if successful.
# @returns undef if successful and net_elems is given
sub _extract_netpath_elements {
my $logger = get_logger("");
my ($self, $netpath, $netpath_elements) = @_;
if (!defined($netpath) || "$netpath" eq "") {
return "Can not parse an empty net.";
}
sub _split_path {
my $path = shift;
my $hiersep = HIERSEP;
my @net_split;
# check if escaped identifiers are present
if ($netpath =~ /\\/) {
if ($path =~ /\\/) {
my $idx = 0;
# walk through string
# check if character at offset is backslash
......@@ -1198,22 +1198,45 @@ sub _extract_netpath_elements {
# after space (or beginning, if no backslash) search for the HIERSEP
# if no HIERSEP, this is the net name
# push that substring
while($idx < length($netpath)) {
while($idx < length($path)) {
my $after_space = $idx;
if (substr($netpath,$idx,1) eq "\\") {
$after_space = index($netpath,' ',$idx);
if (substr($path,$idx,1) eq "\\") {
$after_space = index($path,' ',$idx);
return "Malformed extended identifier: missing trailing space as delimiter" if ($after_space == -1);
}
my $end = index($netpath,HIERSEP,$after_space);
$end = length($netpath) if ($end == -1);
push (@net_split, substr($netpath,$idx,$end-$idx));
my $end = index($path,HIERSEP,$after_space);
$end = length($path) if ($end == -1);
push (@net_split, substr($path,$idx,$end-$idx));
$idx = $end+1;
}
} else {
# if not, we can split easily
@net_split = split(/\Q$hiersep\E/, $netpath);
@net_split = split(/\Q$hiersep\E/, $path);
}
return @net_split;
}
## @method private _extract_netpath_elements($netpath)
# @brief extracts the module name and net name from a given net path.
#
# @param netpath the hierarchical PATH|TO|netname; separator according to constant HIERSEP
# @param netpath_elements (optional) a hashref to store found elements into
#
# @returns STRING if an error occurred
# @returns HASHREF with the keys 'mod_name', 'net_string' if successful.
# @returns undef if successful and net_elems is given
sub _extract_netpath_elements {
my $logger = get_logger("");
my ($self, $netpath, $netpath_elements) = @_;
if (!defined($netpath) || "$netpath" eq "") {
return "Can not parse an empty net.";
}
my $hiersep = HIERSEP;
my @net_split = _split_path($netpath);
if (@net_split < 2) {
return "Net description is not complete: <toplevel_mod>[|<cell>]|<net name>"
}
......
; FIJI::ConfigSorted 0.1
; Tue Mar 22 15:57:15 2016
; Wed Apr 27 13:10:02 2016
[CONSTS]
BAUDRATE=115200
CFGS_PER_MSG=2
CLOCK_NET=top/clk
CLOCK_NET="top/clk"
FAULT_DETECT_1_EN=0
FAULT_DETECT_1_INVERT=0
FAULT_DETECT_1_NAME=
FAULT_DETECT_1_NAME=""
FAULT_DETECT_2_EN=0
FAULT_DETECT_2_INVERT=0
FAULT_DETECT_2_NAME=
FAULT_DETECT_2_NAME=""
FIU_CFG_BITS=3
FIU_NUM=1
FREQUENCY=50000000
......@@ -26,7 +26,7 @@ RESET_DUT_IN_DURATION=1
RESET_DUT_IN_EN=0
RESET_DUT_OUT_ACTIVE=1
RESET_DUT_OUT_EN=0
RESET_DUT_OUT_NAME=
RESET_DUT_OUT_NAME=""
RESET_EXT_ACTIVE=1
RESET_EXT_EN=0
RESET_EXT_IN_NAME=s_fiji_reset_i
......@@ -35,17 +35,17 @@ SYNTHESIS_TOOL=SYNPLIFY_PRO
TIMER_WIDTH=4
TRIGGER_DUT_ACTIVE=1
TRIGGER_DUT_EN=0
TRIGGER_DUT_NAME=
TRIGGER_DUT_NAME=""
TRIGGER_EXT_ACTIVE=1
TRIGGER_EXT_EN=0
TRIGGER_EXT_IN_NAME=s_fiji_trigger_ext_i
TX_OUT_NAME=s_fiji_tx_o
[FIU0]
DRIVER_PATH=top/~w
DRIVER_PATH="top/n=~w"
DRIVER_TYPE=ASSIGN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x0
NET_NAME=top/n
NET_NAME="top/n"
; FIJI::ConfigSorted 0.1
; Tue Mar 22 15:56:48 2016
; Wed Apr 27 13:08:36 2016
[CONSTS]
BAUDRATE=115200
CFGS_PER_MSG=2
CLOCK_NET=top/clk
CLOCK_NET="top/clk"
FAULT_DETECT_1_EN=0
FAULT_DETECT_1_INVERT=0
FAULT_DETECT_1_NAME=
FAULT_DETECT_1_NAME=""
FAULT_DETECT_2_EN=0
FAULT_DETECT_2_INVERT=0
FAULT_DETECT_2_NAME=
FAULT_DETECT_2_NAME=""
FIU_CFG_BITS=3
FIU_NUM=1
FREQUENCY=50000000
......@@ -26,7 +26,7 @@ RESET_DUT_IN_DURATION=1
RESET_DUT_IN_EN=0
RESET_DUT_OUT_ACTIVE=1
RESET_DUT_OUT_EN=0
RESET_DUT_OUT_NAME=
RESET_DUT_OUT_NAME=""
RESET_EXT_ACTIVE=1
RESET_EXT_EN=0
RESET_EXT_IN_NAME=s_fiji_reset_i
......@@ -35,17 +35,17 @@ SYNTHESIS_TOOL=SYNPLIFY_PRO
TIMER_WIDTH=4
TRIGGER_DUT_ACTIVE=1
TRIGGER_DUT_EN=0
TRIGGER_DUT_NAME=
TRIGGER_DUT_NAME=""
TRIGGER_EXT_ACTIVE=1
TRIGGER_EXT_EN=0
TRIGGER_EXT_IN_NAME=s_fiji_trigger_ext_i
TX_OUT_NAME=s_fiji_tx_o
[FIU0]
DRIVER_PATH=top/w
DRIVER_PATH="top/n=w"
DRIVER_TYPE=ASSIGN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x0
NET_NAME=top/n[0]
NET_NAME="top/n[0]"
; FIJI::ConfigSorted 0.1
; Fri Apr 1 19:28:56 2016
; Wed Apr 27 13:08:30 2016
[CONSTS]
BAUDRATE=115200
CFGS_PER_MSG=2
CLOCK_NET=top/clk
CLOCK_NET="top/clk"
FAULT_DETECT_1_EN=0
FAULT_DETECT_1_INVERT=0
FAULT_DETECT_1_NAME=
FAULT_DETECT_1_NAME=""
FAULT_DETECT_2_EN=0
FAULT_DETECT_2_INVERT=0
FAULT_DETECT_2_NAME=
FAULT_DETECT_2_NAME=""
FIU_CFG_BITS=3
FIU_NUM=1
FREQUENCY=50000000
......@@ -26,7 +26,7 @@ RESET_DUT_IN_DURATION=1
RESET_DUT_IN_EN=0
RESET_DUT_OUT_ACTIVE=1
RESET_DUT_OUT_EN=0
RESET_DUT_OUT_NAME=
RESET_DUT_OUT_NAME=""
RESET_EXT_ACTIVE=1
RESET_EXT_EN=0
RESET_EXT_IN_NAME=s_fiji_reset_i
......@@ -35,17 +35,17 @@ SYNTHESIS_TOOL=SYNPLIFY_PRO
TIMER_WIDTH=4
TRIGGER_DUT_ACTIVE=1
TRIGGER_DUT_EN=0
TRIGGER_DUT_NAME=
TRIGGER_DUT_NAME=""
TRIGGER_EXT_ACTIVE=1
TRIGGER_EXT_EN=0
TRIGGER_EXT_IN_NAME=s_fiji_trigger_ext_i
TX_OUT_NAME=s_fiji_tx_o
[FIU0]
DRIVER_PATH=top/w
DRIVER_PATH="top/n=w"
DRIVER_TYPE=ASSIGN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x0
NET_NAME=top/n[0]
NET_NAME="top/n[0]"
; FIJI::ConfigSorted 0.1
; Wed Apr 6 11:44:36 2016
; Wed Apr 27 13:10:12 2016
[CONSTS]
BAUDRATE=115200
......@@ -42,7 +42,7 @@ TRIGGER_EXT_IN_NAME=s_fiji_trigger_ext_i
TX_OUT_NAME=s_fiji_tx_o
[FIU0]
DRIVER_PATH="top/{rev1[0:15]}"
DRIVER_PATH="top/rev2={rev1[0:15]}"
DRIVER_TYPE=ASSIGN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x0
......
; FIJI::ConfigSorted 0.1
; Thu Mar 24 15:35:13 2016
; Wed Apr 27 13:07:51 2016
[CONSTS]
BAUDRATE=115200
CFGS_PER_MSG=2
CLOCK_NET=top/clk
CLOCK_NET="top/clk"
FAULT_DETECT_1_EN=0
FAULT_DETECT_1_INVERT=0
FAULT_DETECT_1_NAME=
FAULT_DETECT_1_NAME=""
FAULT_DETECT_2_EN=0
FAULT_DETECT_2_INVERT=0
FAULT_DETECT_2_NAME=
FAULT_DETECT_2_NAME=""
FIU_CFG_BITS=3
FIU_NUM=1
FREQUENCY=50000000
......@@ -26,7 +26,7 @@ RESET_DUT_IN_DURATION=1
RESET_DUT_IN_EN=0
RESET_DUT_OUT_ACTIVE=1
RESET_DUT_OUT_EN=0
RESET_DUT_OUT_NAME=
RESET_DUT_OUT_NAME=""
RESET_EXT_ACTIVE=1
RESET_EXT_EN=0
RESET_EXT_IN_NAME=s_fiji_reset_i
......@@ -35,14 +35,14 @@ SYNTHESIS_TOOL=SYNPLIFY_PRO
TIMER_WIDTH=4
TRIGGER_DUT_ACTIVE=1
TRIGGER_DUT_EN=0
TRIGGER_DUT_NAME=
TRIGGER_DUT_NAME=""
TRIGGER_EXT_ACTIVE=1
TRIGGER_EXT_EN=0
TRIGGER_EXT_IN_NAME=s_fiji_trigger_ext_i
TX_OUT_NAME=s_fiji_tx_o
[FIU0]
DRIVER_PATH="top/~\\****w**** "
DRIVER_PATH="top/\\++++n++++ =~\\****w**** "
DRIVER_TYPE=ASSIGN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x7
......
; FIJI::ConfigSorted 0.1
; Tue Mar 22 15:57:10 2016
; Wed Apr 27 13:10:58 2016
[CONSTS]
BAUDRATE=115200
CFGS_PER_MSG=2
CLOCK_NET=top/clk
CLOCK_NET="top/clk"
FAULT_DETECT_1_EN=0
FAULT_DETECT_1_INVERT=0
FAULT_DETECT_1_NAME=
FAULT_DETECT_1_NAME=""
FAULT_DETECT_2_EN=0
FAULT_DETECT_2_INVERT=0
FAULT_DETECT_2_NAME=
FAULT_DETECT_2_NAME=""
FIU_CFG_BITS=3
FIU_NUM=1
FREQUENCY=50000000
......@@ -26,7 +26,7 @@ RESET_DUT_IN_DURATION=1
RESET_DUT_IN_EN=0
RESET_DUT_OUT_ACTIVE=1
RESET_DUT_OUT_EN=0
RESET_DUT_OUT_NAME=
RESET_DUT_OUT_NAME=""
RESET_EXT_ACTIVE=1
RESET_EXT_EN=0
RESET_EXT_IN_NAME=s_fiji_reset_i
......@@ -35,17 +35,17 @@ SYNTHESIS_TOOL=SYNPLIFY_PRO
TIMER_WIDTH=4
TRIGGER_DUT_ACTIVE=1
TRIGGER_DUT_EN=0
TRIGGER_DUT_NAME=
TRIGGER_DUT_NAME=""
TRIGGER_EXT_ACTIVE=1
TRIGGER_EXT_EN=0
TRIGGER_EXT_IN_NAME=s_fiji_trigger_ext_i
TX_OUT_NAME=s_fiji_tx_o
[FIU0]
DRIVER_PATH=top/~w
DRIVER_PATH="top/n=~w"
DRIVER_TYPE=ASSIGN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x0
NET_NAME=top/n
NET_NAME="top/n"
; FIJI::ConfigSorted 0.1
; Tue Mar 22 15:57:24 2016
; Wed Apr 27 13:08:42 2016
[CONSTS]
BAUDRATE=115200
CFGS_PER_MSG=2
CLOCK_NET=top/clk
CLOCK_NET="top/clk"
FAULT_DETECT_1_EN=0
FAULT_DETECT_1_INVERT=0
FAULT_DETECT_1_NAME=
FAULT_DETECT_1_NAME=""
FAULT_DETECT_2_EN=0
FAULT_DETECT_2_INVERT=0
FAULT_DETECT_2_NAME=
FAULT_DETECT_2_NAME=""
FIU_CFG_BITS=3
FIU_NUM=1
FREQUENCY=50000000
......@@ -26,7 +26,7 @@ RESET_DUT_IN_DURATION=1
RESET_DUT_IN_EN=0
RESET_DUT_OUT_ACTIVE=1
RESET_DUT_OUT_EN=0
RESET_DUT_OUT_NAME=
RESET_DUT_OUT_NAME=""
RESET_EXT_ACTIVE=1
RESET_EXT_EN=0
RESET_EXT_IN_NAME=s_fiji_reset_i
......@@ -35,17 +35,17 @@ SYNTHESIS_TOOL=SYNPLIFY_PRO
TIMER_WIDTH=4
TRIGGER_DUT_ACTIVE=1
TRIGGER_DUT_EN=0
TRIGGER_DUT_NAME=
TRIGGER_DUT_NAME=""
TRIGGER_EXT_ACTIVE=1
TRIGGER_EXT_EN=0
TRIGGER_EXT_IN_NAME=s_fiji_trigger_ext_i
TX_OUT_NAME=s_fiji_tx_o
[FIU0]
DRIVER_PATH=top/~i
DRIVER_PATH="top/w=~i"
DRIVER_TYPE=ASSIGN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x0
NET_NAME=top/w
NET_NAME="top/w"
; FIJI::ConfigSorted 0.1
; Tue Mar 22 15:57:21 2016
; Wed Apr 27 13:08:14 2016
[CONSTS]
BAUDRATE=115200
CFGS_PER_MSG=2
CLOCK_NET=top/clk
CLOCK_NET="top/clk"
FAULT_DETECT_1_EN=0
FAULT_DETECT_1_INVERT=0
FAULT_DETECT_1_NAME=
FAULT_DETECT_1_NAME=""
FAULT_DETECT_2_EN=0
FAULT_DETECT_2_INVERT=0
FAULT_DETECT_2_NAME=
FAULT_DETECT_2_NAME=""
FIU_CFG_BITS=3
FIU_NUM=1
FREQUENCY=50000000
......@@ -26,7 +26,7 @@ RESET_DUT_IN_DURATION=1
RESET_DUT_IN_EN=0
RESET_DUT_OUT_ACTIVE=1
RESET_DUT_OUT_EN=0
RESET_DUT_OUT_NAME=
RESET_DUT_OUT_NAME=""
RESET_EXT_ACTIVE=1
RESET_EXT_EN=0
RESET_EXT_IN_NAME=s_fiji_reset_i
......@@ -35,17 +35,17 @@ SYNTHESIS_TOOL=SYNPLIFY_PRO
TIMER_WIDTH=4
TRIGGER_DUT_ACTIVE=1
TRIGGER_DUT_EN=0
TRIGGER_DUT_NAME=
TRIGGER_DUT_NAME=""
TRIGGER_EXT_ACTIVE=1
TRIGGER_EXT_EN=0
TRIGGER_EXT_IN_NAME=s_fiji_trigger_ext_i
TX_OUT_NAME=s_fiji_tx_o
[FIU0]
DRIVER_PATH=top/~i
DRIVER_PATH="top/w=~i"
DRIVER_TYPE=ASSIGN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x0
NET_NAME=top/w[0]
NET_NAME="top/w[0]"
; FIJI::ConfigSorted 0.1
; Tue Mar 22 15:57:18 2016
; Wed Apr 27 13:08:24 2016
[CONSTS]
BAUDRATE=115200
CFGS_PER_MSG=2
CLOCK_NET=top/clk
CLOCK_NET="top/clk"
FAULT_DETECT_1_EN=0
FAULT_DETECT_1_INVERT=0
FAULT_DETECT_1_NAME=
FAULT_DETECT_1_NAME=""
FAULT_DETECT_2_EN=0
FAULT_DETECT_2_INVERT=0
FAULT_DETECT_2_NAME=
FAULT_DETECT_2_NAME=""
FIU_CFG_BITS=3
FIU_NUM=1
FREQUENCY=50000000
......@@ -26,7 +26,7 @@ RESET_DUT_IN_DURATION=1
RESET_DUT_IN_EN=0
RESET_DUT_OUT_ACTIVE=1
RESET_DUT_OUT_EN=0
RESET_DUT_OUT_NAME=
RESET_DUT_OUT_NAME=""
RESET_EXT_ACTIVE=1
RESET_EXT_EN=0
RESET_EXT_IN_NAME=s_fiji_reset_i
......@@ -35,17 +35,17 @@ SYNTHESIS_TOOL=SYNPLIFY_PRO
TIMER_WIDTH=4
TRIGGER_DUT_ACTIVE=1
TRIGGER_DUT_EN=0
TRIGGER_DUT_NAME=
TRIGGER_DUT_NAME=""
TRIGGER_EXT_ACTIVE=1
TRIGGER_EXT_EN=0
TRIGGER_EXT_IN_NAME=s_fiji_trigger_ext_i
TX_OUT_NAME=s_fiji_tx_o
[FIU0]
DRIVER_PATH=top/~i[0]
DRIVER_PATH="top/w[0]=~i[0]"
DRIVER_TYPE=ASSIGN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x0
NET_NAME=top/w[0]
NET_NAME="top/w[0]"
; FIJI::ConfigSorted 0.1
; Fri Apr 1 19:37:06 2016
; Wed Apr 27 13:09:56 2016
[CONSTS]
BAUDRATE=115200
CFGS_PER_MSG=2