Commit 613ba681 authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
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Extended userguide

parent f4ebba73
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@BOOK{adams2007hitchhiker,
title = {The Hitchhiker's Guide to the Galaxy},
publisher = {Random House Publishing Group},
year = {2007},
author = {Adams, Douglas},
series = {Hitchhiker's Guide to the Galaxy},
isbn = {9780307417138}
@misc{oregano8051,
title = {{MC8051 IP Core -- Overview V1.3}},
year = {2013},
author = {{Oregano Systems}},
howpublished = {\url{http://www.oreganosystems.at/}}
}
\section{Introduction}
Silence bibtex error \cite{adams2007hitchhiker}
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%Silence bibtex error \cite{adams2007hitchhiker}
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\section{FIJI Setup Tool}
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\section{FIJI Setup Tool}
\begin{figure}[h]
\centering
\includegraphics[width=0.85\linewidth]{img/fiji_setup_screenshot.png}
\caption{FIJI Setup Tool}
\end{figure}
\ No newline at end of file
\section{Implementation}
\subsection{Synthesis using Synplify Pro}
\subsection{Place-and-Route using Quartus II 13.0}
\begin{enumerate}
\item \texttt{cd} into \texttt{mc0851\_demo/fiji\_test\_1/quartus}
\item \texttt{\$ cp ../../quartus/pins.qsf .} \\
\texttt{\$ cp ../../synp/fpga\_top\_cyclonev\_mc8051\_rom\_quartus\_altsyncram\_component.mif .} \\
\texttt{\$ cp ../synp/rev\_1/fiji\_test\_1.vqm .} \\
(\texttt{.} = \texttt{mc0851\_demo/fiji\_test\_1/quartus})
\item Launch Quartus GUI
\item Create new project \textit{``fiji\_test\_1''}
\begin{itemize}
\item Set top-level entity to \textit{``fiji\_top''}
\item Add file \textit{./fiji\_test\_1.vqm}
\item Add file \textit{./fiji\_top.sdc}
\item Set Device Family to \textit{Cyclone V}
\item Set Device to \textit{5CSXFC6D6F31C8ES}
\end{itemize}
5. Import the assignments in \textit{pins.qsf} and \textit{new\_pins.qsf} into the new project \\
(via Assignments $\rightarrow$ Import Assignments)
\end{enumerate}
\textbf{Attention}: The timing constraints in \textit{./fiji\_top.sdc} have been already created
for the instrumented netlist. In a ``real'' flow, these would be created by the
user or imported from Synplify.
\textbf{Note}: The pin constraints in \textit{./new\_pins.qsf} have been already created for the
final FIJI design. In a ``real'' flow, these would be created ``on the fly'' by the
user.
Blabla
\section{Runtime Fault Injection Tool}
\ No newline at end of file
\section{Runtime Fault Injection Tool}
Blabla
\begin{figure}[h]
\centering
\includegraphics[width=0.85\linewidth]{img/fiji_download_sequence_screenshot.png}
\caption{FIJI Download Tool: Sequence Mode}
\end{figure}
BlablaBlabla
\begin{figure}[h]
\centering
\includegraphics[width=0.85\linewidth]{img/fiji_download_manual_screenshot.png}
\caption{FIJI Download Tool: Manual Mode}
\end{figure}
BlablaBlablaBlabla
\begin{figure}[h]
\centering
\includegraphics[width=0.85\linewidth]{img/fiji_download_random_screenshot.png}
\caption{FIJI Download Tool: Random Mode}
\end{figure}
BlablaBlablaBlablaBlabla
\ No newline at end of file
\section{Demo: MC8051}
\subsection{Original Design}
This demo design is intended for use with the \textit{Cyclone V SoC FPGA Development Kit}
from Altera with the HSMC breakout board attached.
The original design contains an open-source MC8051 microcontroller core \cite{oregano8051},
BRAM, two $I^{2}C$ masters, and some custom error-checking logic. The error-checking
logic monitors the $I^{2}C$ bus, the stack pointer, and the program counter of
the MC8051 core. The software communicates with the LCD display and an RTC via $I^{2}C$. The 1's
position of the seconds output by the RTC is displayed one-hot encoded on the
ten green LEDs on the HSMC breakout board. If the error checking logic encounters
errors, red LEDs on the HSMC breakout board, corresponding to the error ID, are
switched on. Once an error checking unit is triggered, it can only be brought to
initial condition by performing a reset via Button S10 (CPU RST). Depending on the
switch position of SW1 -- FPGA0, an interrupt to the microcontroller is generated
(towards board edge) or not (away from board edge).
\subsection{Setup}
\subsubsection{Directories}
\subsubsection{Hardware}
Board setup:
\begin{itemize}
\item Switch positions:
\begin{itemize}
\item SW2: All away from board edge
\item SW3 (MSEL): All towards board edge
\item SW4 (JTAG ENABLE): HPS and FPGA away from board edge, HSMC and MAX towards board edge
\item J6 (HPS SEL): Short
\item J7 (JTAG SEL): Short
\item J1: Short
\item J16: Open
\item J31: Open
\item J26 (CLKSEL0): Mid and left (Towards HSMC)
\item J27 (CLKSEL1): Mid and right (Away from HSMC)
\item J28 (BOOTSEL0): Mid and left
\item J29 (BOOTSEL1): Mid and right
\item J30 (BOOTSEL2): Mid and left
\end{itemize}
\item Connect the HSMC breakout board that came with the development kit
\item Connect a 2.5V Serial TTL cable to the HSMC breakout board:
\begin{itemize}
\item Connect \textit{Ground} to the TP1 GND pin on the breakout board
\item Connect \textit{TXD} to J1 -- pin 3
\item Connect \textit{RXD} with J1 -- pin 5
\item Leave \textit{\#RTS} open
\item Connect \textit{\#CTS} to GND (or leave open if your cable
pulls it to a level)
\item If your cable requires an I/O voltage input (e.g., FTDI TTL-232R-VIP),
connect the correspondig wire to J23 (JTAG) -- pin 4 on
the main development board. This is a 2.5V output.
\end{itemize}
\end{itemize}
\subsubsection{Run setup}
\texttt{\$ fiji\_setup.pl mc8051\_demo/fiji\_test\_1/fiji.cfg}
\subsection{Instrumentation}
\begin{verbatim}
$ perl fiji_instrument.pl --fiji_settings_file=mc8051_demo/fiji_test_1/fiji.cfg \
--netlist_file=mc8051_demo/synp/fpga_top.vqm \
--file_prefix=fiji_demo
\end{verbatim}
\subsection{Implementation}
\subsubsection{Synthesis using Synplify Pro}
\begin{enumerate}
\item Change directory to \texttt{mc8051\_demo/fiji\_test\_1/synp}
\item \begin{verbatim}
$ cp ../../synp/fpga_top.fdc .
$ cp ../fiji/fiji_demo_synplify_quartus_constraints.fdc .
$ cp ../../synp/fpga_top_cyclonev_mc8051_rom_quartus_altsyncram_component.mif .
(. = mc0851_demo/fiji_test_1/synp)
\end{verbatim}
\item Open Synplify GUI
\item Create a new project \textit{fiji\_test\_1.prj}
\item Implementation Options:
\begin{itemize}
\item Device Tab:
\begin{itemize}
\item Set \textit{Altera Cyclone V} as Technology
\item Set \textit{5CSXFC6D6} as Part
\item Set \textit{FC31} as Package
\item Set \textit{-8ES} as Speed
\end{itemize}
\item Constraints Tab: \\
Set Clock Frequency to 50 Mhz (PLL clock frequencies are derived
automatically from instantiation)
\item Implementation Results Tab:
\begin{itemize}
\item Set Quartus Version to Quartus II 13.0
\item (Set Result Base Name to \textit{fiji\_test\_1})
\end{itemize}
\item VHDL tab: \\
Set \textit{fiji\_top} as the top level entity
\end{itemize}
\item Add files:
\begin{verbatim}
./fpga_top.fdc
../fiji/fiji_demo_config_pkg.vhd
../fiji/fiji_demo_instrumented.vqm
../fiji/fiji_demo_wrapper.vhd
../../../../hw/rtl/*.vhd
\end{verbatim}
\todo{Add RTL to git?}
\item Edit \texttt{./fpga\_top.fdc} in Synplify:
When using SCOPE editor: Ignore errors at the beginning.
Prefix all Multicycle paths with \textit{i\_DUT.} after the \textit{n:} (in Tab Delay Paths)
Save, exit editor
\item Run (\keystroke{F8})
\end{enumerate}
\subsubsection{Place-and-Route using Quartus II 13.0}
\begin{enumerate}
\item \texttt{cd} into \texttt{mc8051\_demo/fiji\_test\_1/quartus}
\item \texttt{\$ cp ../../quartus/pins.qsf .} \\
\texttt{\$ cp ../../synp/fpga\_top\_cyclonev\_mc8051\_rom\_quartus\_altsyncram\_component.mif .} \\
\texttt{\$ cp ../synp/rev\_1/fiji\_test\_1.vqm .} \\
(\texttt{.} = \texttt{mc0851\_demo/fiji\_test\_1/quartus})
\item Launch Quartus GUI
\item Create new project \textit{``fiji\_test\_1''}
\begin{itemize}
\item Set top-level entity to \textit{``fiji\_top''}
\item Add file \textit{./fiji\_test\_1.vqm}
\item Add file \textit{./fiji\_top.sdc}
\item Set Device Family to \textit{Cyclone V}
\item Set Device to \textit{5CSXFC6D6F31C8ES}
\end{itemize}
\item Import the assignments in \textit{pins.qsf} and \textit{new\_pins.qsf} into the new project \\
(via Assignments $\rightarrow$ Import Assignments)
\end{enumerate}
\textbf{Attention}: The timing constraints in \textit{./fiji\_top.sdc} have been already created
for the instrumented netlist. In a ``real'' flow, these would be created by the
user or imported from Synplify.
\textbf{Note}: The pin constraints in \textit{./new\_pins.qsf} have been already created for the
final FIJI design. In a ``real'' flow, these would be created ``on the fly'' by the
user.
\subsection{Runtime fault injection}
\begin{enumerate}
\item Download the FPGA bitstream via Quartus Downloader
\item \begin{verbatim}
$ perl fiji_download_gui.pl mc8051_demo/fiji_test_1/fiji_demo_download.cfg \
mc8051_demo/fiji_test_1/fiji_demo_test.tst
\end{verbatim}
\item Execute tests:
\begin {itemize}
\item Pre-defined sequence in \texttt{fiji\_demo\_test.tst}
\item Manual tests
\item Random tests
\end {itemize}
\end{enumerate}
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......@@ -21,6 +21,7 @@
\usepackage{enumerate}
\usepackage{amsmath,amssymb,amsfonts,amstext}
\usepackage{keystroke}
\usepackage{textcomp}
\usepackage{multirow}
......@@ -254,6 +255,7 @@
\input{content/04-instrumentation.tex}
\input{content/05-synthesis.tex}
\input{content/06-runtime.tex}
\input{content/07-demo.tex}
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\newpage
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