Commit 5d63c33e authored by Stefan Tauner's avatar Stefan Tauner
Browse files

Refine TRM

parent d6ba883f
......@@ -587,7 +587,7 @@ BEGIN {
default => "s_fiji_rx_i",
phases_opt => [qw(instrument download)],
group => "general_control",
order => 30,
order => 11,
},
TX_OUT_NAME => {
description => "TX port name",
......@@ -597,7 +597,7 @@ BEGIN {
phases_opt => [qw(instrument download)],
default => "s_fiji_tx_o",
group => "general_control",
order => 40,
order => 12,
},
OPTIMIZATIONS => {
description => "Optimizations",
......
......@@ -8,31 +8,34 @@ The \ac{FIC} is connected with a host computer via a \ac{UART} unit to
allow remote changes of the \ac{FIU} configurations and control the
execution of the system.
\Cref{fig:fi_seq} depicts a complete \ac{FIJI} system comprising the \ac{DUT} (bottom right), together with the \ac{FIJI} logic (top right) in an FPGA connected to a controlling host computer (left).
\begin{figure}[ht]
\centering
\includegraphics[width=0.85\linewidth]{../tex_common/img/Overview.pdf}
\caption{FIJI Overview}
\label{fig:fiji_overview}
\end{figure}
The FIUs can inject the following:
The \acp{FIU} can inject the following:
\begin{itemize}
\item Original signal (no fault)
\item Stuck at 0 level
\item Stuck at 1 level
\item Original signal delayed by one clock (models delay faults)
\item Inversion of the original signal for a single clock cycle (models single event upsets)
\item Inversion of the original signal for a single clock cycle (models \acp{SEU})
\item Pseudo-random data (models stuck-open faults)
\end{itemize}
There are several reset and triggering options: Either the \ac{FIC} can (on the
host's command) reset the \ac{DUT}, or the \ac{DUT} may reset the FI logic.
Naturally either of these options can be selected at build time to prevent
Naturally only either one of these options can be selected at build time to prevent
infinite reset loops. Additionally, the FI logic’s reset may be routed
to an I/O pin to be activated externally. Injected faults can be deferred
until a trigger signal fires. The source of this signal can be changed
at runtime and may be an external pin or a signal from the \ac{DUT}. Optionally,
two signals can be selected to provide fault-detection information.
two signals of the \ac{DUT} can be selected to provide the \ac{FIC} with fault-detection information.
Which nets in the \ac{DUT} are suitable to provide this information depends
on the application. If the application contains some kind of fault-detection logic,
for example, the outputs of this module can be used.
......@@ -42,12 +45,12 @@ for example, the outputs of this module can be used.
The whole configuration and injection process can be divided into five
phases. The execution of these phases is handled by the \ac{FIC} based on
the arrival of configuration data from the host, a timer and a trigger signal.
A graphical representation of these phases is shown in Figure~\ref{fig:fi_seq}.
A graphical representation of these phases is shown in \Cref{fig:fi_seq}.
First (in the \textit{CONF} phase), the host has to transmit a new configuration
to the hardware. The \ac{FIC} stores parts of the configuration internally
and forwards the parts relevant to the FIUs into temporary registers
within the FIUs. When the previously active injection process ends,
within the \acp{FIU}. When the previously active injection process ends,
the \ac{FIC} can start a new one according to this buffered configuration information.
At the begin of the second phase (\textit{WAIT}) the \ac{FIC} resets the \ac{DUT}, if
......@@ -58,11 +61,11 @@ The duration of the \textit{COUNT} phase depends on the configuration value sent
by the host. This allows to precisely time the starting point of the
injection of the first fault pattern relatively to the trigger
(if activated) or to the reception of the respective configuration data.
When the timer finishes counting down, the \ac{FIC} instructs the FIUs to
When the timer finishes counting down, the \ac{FIC} instructs the \acp{FIU} to
adopt the first fault pattern and starts the \textit{FAULT1} phase: The timer
counts down from a second configuration value, while the first fault
pattern is active. When the timer finishes counting down the second
time, the \ac{FIC} instructs the FIUs to activate the second fault pattern
time, the \ac{FIC} instructs the \acp{FIU} to activate the second fault pattern
and thus starts \textit{FAULT2}. This pattern remains active until the next
configuration is received and activated.
......@@ -88,7 +91,7 @@ netlist of the original design. Within this instrumented netlist all
previously selected nets are broken up and routed out of the entity.
The script also generates a new top-level wrapper that instantiates the
instrumented design and channels the exported signals through dedicated
FIUs and back into the user design. The resulting design is then synthesized
\acp{FIU} and back into the user design. The resulting design is then synthesized
again and is then subjected to P\&R to create the final FPGA configuration
bitstream.
At this point the design is ready to be installed in an FPGA and can
......
\section{Protocol}
The communication between the hardware and fiji\_download.pl uses a
The communication between the hardware and the \texttt{fiji\_ee*.pl} tools uses a
UART protocol with 8N1 configuration (8 data bits, 1 stop bit, no parity).
Each communication direction uses its own message format.
The baud rate is configurable (in \texttt{fiji\_setup.pl}) with a default of 115200.
Each communication direction uses its own message format as explained in the next two subsections.
\subsection{FIC to Host}
\label{sec:f2h}
The data sent by the FIC to the host serves to inform the host about important events and errors on the hardware side.
The data sent by the \ac{FIC} to the host serves to inform the host about important events and errors on the hardware side.
All packets consist of a single byte with three possible types encoded in bits 5 and 6 as depicted in \Cref{fig:f2h}.
\begin{figure}[ht]
\centering
......@@ -17,16 +18,15 @@ The data sent by the FIC to the host serves to inform the host about important e
\label{fig:f2h}
\end{figure}
There is a single type of packet that consists of a single byte as depicted in Figure~\ref{fig:f2h}.
Bit 8 is used as even parity bit (i.e., it needs to be set iff an uneven
number of remaining bits are set).
Bits 5 and 6 encode message types that inform the host about events that
The three message types denoted by bits 5 and 6 inform the host about events that
can happen at the transition between two execution phases:
\begin{itemize}
\item At the end of the configuration phase the FIC acknowledges the
\item At the end of the configuration phase the \ac{FIC} acknowledges the
successful reception of the configuration data by sending a
\textit{CONF\_DONE} message with all error bits set to zero.
If there were any of the noted errors while the configuration
......@@ -34,12 +34,12 @@ can happen at the transition between two execution phases:
\item When the injection of \textit{FAULT1} starts, the temporary registers
storing the configuration are freed and can be filled again
by the host. At that point the FIC sends a \textit{READY} message
by the host. At that point the \ac{FIC} sends a \textit{READY} message
to inform the host that injection has been activated and that
a new configuration can be received by the FIC.
a new configuration can be received by the \ac{FIC}.
\item If the injection phase \textit{FAULT1} ends before the host
has sent a new configuration, the FIC indicates this case with
has sent a new configuration, the \ac{FIC} indicates this case with
an \textit{UNDERRUN} message. In this case the exact timing
of later injections depend on the point in time when the
following configuration is received.
......@@ -60,23 +60,24 @@ The lowest three bits denote possible errors when receiving configuration data f
They are only guaranteed to be valid in \textit{CONF\_DONE} messages as noted above.
\subsection{Host to FIC}
\label{sec:h2f}
The packets sent by the host are more complex. They can be separated into
two major parts: configuration data for the FIUs and information destined
for the FIC itself.
The packets sent by the host are more complex as evident from \Cref{fig:h2f}.
They can be separated into two major parts:
configuration data for the \acp{FIU} and information destined for the \ac{FIC} itself.
First, the configuration bits for the FIUs are transmitted in a serialized
First, the configuration bits for the \acp{FIU} are transmitted in a serialized
fashion: To end the actual data at a byte boundary the first bits are used
as stuffing, if need be. Then the data for the last FIU follows succeeded
by the configuration for the FIU before the last etc. At byte borders the
data of a single FIU is simply split and continued to be transmitted in
the next byte. Each 6-bit FIU configuration consists of two 3-bit fault
as stuffing, if need be. Then the data for the last \ac{FIU} follows succeeded
by the configuration for the \ac{FIU} before the last etc. At byte borders the
data of a single \ac{FIU} is simply split and continued to be transmitted in
the next byte. Each 6-bit \ac{FIU} configuration consists of two 3-bit fault
patterns, of which the pattern transferred first (1) is activated in phase
\textit{FAULT1}, while the second pattern (2) is activated in \textit{FAULT2}.
Each bit pattern is transferred with the least significant bit first.
The remaining part of the message contains control information destined
to the FIC itself. All multi-byte values are transmitted in little-endian
to the \ac{FIC} itself. All multi-byte values are transmitted in little-endian
(on the byte and bit level). At first, the load values of the two
timers for the FAULT phases (duration $t_1$ for \textit{FAULT1} and duration $t_2$
for \textit{FAULT2} respectively) are transmitted. The number of bytes
......@@ -84,16 +85,17 @@ required depends on the width of the timers and can vary between designs.
Following the timer values a bit field is sent to control the following properties:
\begin{itemize}
\item Bit 0 (TE) indicates if the FIC should stay in the \textit{WAIT} phase until the trigger is detected.
\item Bit 1 (XT) decides the triggers source: either the external trigger input, or the internal trigger from the DUT.
\item Bit 2 (R) specifies if the user design should be reset by the FIC at the beginning of the \textit{WAIT} phase.
\item Bit 7 (U) specifies that the current configuration shall not be activated. This can be used to retrieve
\begin{description}[leftmargin=5.5em,style=sameline,font={\normalfont}]
\item [Bit 0 (\textbf{TE})] indicates if the \ac{FIC} should stay in the \textit{WAIT} phase until the trigger is detected.
\item [Bit 1 (\textbf{XT})] decides the trigger's source: either the external trigger input (if set), or the internal trigger from the DUT (if unset).
\item [Bit 2 (\textbf{R}) ] specifies if the user design should be reset by the \ac{FIC} at the beginning of the \textit{WAIT} phase.
\item [Bit 7 (\textbf{U}) ] specifies that the current configuration shall not be activated. This can be used to retrieve
the state of the Fault Detect signals without interrupting an active \textit{FAULT2} pattern.
\end{itemize}
\end{description}
Then, the 16 bits of the design ID is transmitted to allow the FIC to
check the sent configuration for compatibility.
Then, the 16 bits of the design ID is transmitted to allow the \ac{FIC} to
check the sent configuration for compatibility with the hardware configuration.
Its value is determined at instrumentation time and stored in the \ac{FIJI} Settings to be available during communication.
An 8-bit CRC at the end protects the message against bit flips.
The polynomial used is 0xE0 with an initialization value of 0xFF.
......@@ -102,5 +104,6 @@ The data for the CRC algorithm is input and output as big-endian.
\begin{figure}
\centering
\input{content/protocol_host_to_fic}
\caption{Host to FIC communication message format}
\caption{Host to \ac{FIC} communication message format}
\label{fig:h2f}
\end{figure}
\section{Execution Flow}
%Silence bibtex error \cite{adams2007hitchhiker}
\fixme{move the whole section to the user manual? without knowing how tests are executed a user cannot configure tests appropriately}
\begin{figure}[ht]
\centering
......@@ -9,40 +10,46 @@
\end{figure}
In Figure~\ref{fig:seq} an extract of a longer execution is depicted showing
In \Cref{fig:seq} an extract of a longer execution is depicted showing
some of the possible sequences of events.
First of all, the FIC must acquire a valid configuration consisting of the
packets explained above. If there are any reception errors (frame error, wrong
ID, or CRC mismatch) the FIC nevertheless continues reading in the appropriate
First of all, the \ac{FIC} must acquire a valid configuration as specified in \Cref{sec:h2f}.
If there are any reception errors (frame error, wrong
ID, or CRC mismatch) the \ac{FIC} nevertheless continues reading in the appropriate
amount of frames/bytes for a configuration. Only after the complete reception
of the expected number of bytes the FIC reports the result back to the host. To
of the expected number of bytes the \ac{FIC} reports the result back to the host. To
that end a \textit{CONF\_DONE} message is sent, possibly with some set error bits (see
Section~\ref{sec:f2h}).
\Cref{sec:f2h}).
Upon the successful reception of a configuration, the DUT is reset by the FIC
if requested. The FIC then optionally waits for a trigger signal (again
depending on a configuration setting) and then starts the next phase. The
second and partially visible third execution cycles do not use any triggers and
Upon the successful reception of a configuration, the DUT is reset by the \ac{FIC}
if requested. The \ac{FIC} then optionally waits for a trigger signal (again
depending on a configuration setting) and then starts the next phase.
NB: In \Cref{fig:seq} the
second and partially visible third execution cycle do not use any triggers and
thus have no \textit{WAIT} phases at all.
In the \textit{COUNT} phase the timer counts down duration $t_1$. When the timer expires,
the FIC instructs the FIUs to apply fault pattern 1 and thus possibly enables
the forwarding of faulty signals by the FIUs. At this point the FIC reports
the \ac{FIC} instructs the \acp{FIU} to apply fault pattern 1 and thus possibly enables
the forwarding of faulty signals by the \acp{FIU}. At this point the \ac{FIC} reports
back to the host that transmitting a new configuration is now possible with a
\textit{READY} message. Also, it loads the timer with duration $t_2$. When the timer
expires, the FIC instructs the FIUs to apply fault pattern 2. This pattern
expires, the \ac{FIC} instructs the \acp{FIU} to apply fault pattern 2. This pattern
stays active until the duration $t_1$ of the next configuration has been counted
down.
In other words $t_1$ determines exactly the time between reception of a new configuration or optionally the arrival of a trigger and the start of the first fault.
$t_2$ on the other hand specifies how long this first fault should be active (before fault~2 becomes active).
In the ideal case the host sends a new configuration while duration $t_2$ of the
previous configuration is still in progress. This allows to apply successive
configurations or even fault patterns themselves without a gap. If the new
configuration does not arrive in time, the FIC notifies the host by sending
\textit{UNDERRUN}. It then waits for a new configuration to be downloaded.
configuration does not arrive in time, the \ac{FIC} notifies the host by sending an
\textit{UNDERRUN} message. It then waits for a new configuration to be downloaded.
\subsection{Fault Models}
\fixme{wiederholung von 1. section}
The \acp{FIU} can be configured to forward the following signal types:
\begin{itemize}
\item Original signal (no fault)
......
\section{Tool Flow and Settings}
\label{sec:flow}
The framework is highly configurable and consists of various parts that
require access to configuration parameters (see tables at the end of the chapter for a complete list).
The \ac{FIJI} framework is highly configurable and consists of various parts that
require access to configuration parameters (see the tables in \Cref{sec:consts} for a complete list).
\subsection{FIJI Setup Tool}
The \ac{FIJI} Settings file (usually named fiji.cfg) serves as intermediate
The \ac{FIJI} Settings file (usually named \texttt{fiji.cfg}) serves as intermediate
storage for the parameters and is read by the various tools of the framework.
It is normally created by \texttt{fiji\_setup.pl} from the synthesized netlist of
the user design and input from the user. It acquires information about
......@@ -17,23 +16,24 @@ following data:
\begin{itemize}
\item Name of the clock net within the DUT to be used as input for the FIC and its frequency,
\item UART baud rate,
\item Name for serial RX and TX signals,
\item Width of the timer (determining the maximum time spans of the t1 and t2 durations),
\item Width, polynomial, seed of the linear feedback shift register (LFSR) that is used to generate pseudo randomness,
\item Activation, polarity, name of external reset
\item Activation, polarity, name of DUT-to-FIC reset signal
\item Activation, polarity, name, duration of FIC-to-DUT reset signal
\item Activation, polarity, name of internal trigger input
\item Activation, polarity, name of external trigger input
\item ``FPGA Implementation'' tool (and other target-related information?)
\item Name for serial RX and TX signals
\item Width, polynomial, seed of the \ac{LFSR} that is used to generate pseudo randomness,
\item Activation, polarity, name of the external reset,
\item Activation, polarity, name of the DUT-to-FIC reset signal,
\item Activation, polarity, name, duration of the FIC-to-DUT reset signal,
\item Activation, polarity, name of the internal trigger input,
\item Activation, polarity, name of the external trigger input,
\item Activation, polarity, names of the two fault detection signals,
\item the used ``FPGA Implementation'' tool.
\end{itemize}
\item For each ``faulty'' net (thereby specifying the number of \acp{FIU}
\item For each ``faulty'' net (thereby specifying the number of \acp{FIU})
\begin{itemize}
\item Net name
\item Net driver
\item Fault models (all 5 fault models or one (selected) of them (cf. Table~\ref{tab:faultmodels})
\item Bits of global \ac{LFSR} which should be ANDed to generate the random fault in
stuck-open mode
\item Available fault models: all 5 fault models or only a single (selectable) one of them (cf.\ \Cref{tab:faultmodels})
\item Bits of the global \ac{LFSR} which should be ANDed to generate the random signal in stuck-open mode
\end{itemize}
\end{itemize}
......@@ -56,7 +56,7 @@ Appropriate constraints are added to prevent unwanted optimizations that would i
All runtime configuration is done with \texttt{fiji\_ee.pl} or \texttt{fiji\_ee\_gui.pl}
which communicate with the DUT over a common serial connection. It works with
any type of serial port (e.g. RS-232-compatible ports or USB-based TTL-level
any type of serial port (e.g., RS-232-compatible ports or USB-based TTL-level
adapters) as long as the operating system represents it as such. The scripts
support three modes:
......@@ -86,11 +86,12 @@ There are two major types of blocks allowed:
\begin{itemize}
\item a single \texttt{consts} block specifies various constants for a specific design.
\item for every \ac{FIU} in the setup there is a respective block named \texttt{FIU\textit{<number>}} where \textit{<number>}
\item for every \ac{FIU} in the setup there is a respective block named \texttt{\ac{FIU}\textit{<number>}} where \textit{<number>}
is a strictly increasing integer starting with 0 for the first \ac{FIU} in a design.
\end{itemize}
\subsubsection{Constants}
\label{sec:consts}
Table~\ref{tab:consts} lists all specifiable constants for a design, while
Table~\ref{tab:fiuconsts} explains the settings for each \ac{FIU}. The ``Name''
......
......@@ -38,7 +38,7 @@ For this purpose it contains:
\item a central state machine
\item the duration counter,
\item CRC calculation logic
\item the LFSR,
\item the \ac{LFSR},
\item synchronization and edge detection logic for the trigger signals,
\item registers for the received ID, timer values, and controller configuration.
\end{itemize}
......@@ -49,7 +49,7 @@ The configuration bits specify if the DUT is reset after the configuration
was received, if the FIC waits for the selected trigger signal to transition
from inactive to active (cf. c\_trigger\_dut\_active and c\_trigger\_ext\_active
in Table 6) and which trigger (internal or external) to use.
The LFSR is implemented as a left-shifted Galois type. Thus, the rightmost
The \ac{LFSR} is implemented as a left-shifted Galois type. Thus, the rightmost
bit in the polynomial specified in c\_lfsr\_seed as a global configuration
constant corresponds to $x^1$ and the leftmost bit to $x^{\text{c\_lfsr\_width}}$.
......
% We use an lrbox to define the bytefield first to be able to stuff it into
% a table cell below. The legend is then put into a second cell on the right
% (distance is controlled by the width of the parbox in the left cell.
\newsavebox{\bytefieldbox}
\begin{lrbox}{\bytefieldbox}
\makeatletter
\let\bf@leftcurly=\bsp
\begin{bytefield}[bitwidth=2em]{8}
\bitheader[endianness=big]{0-7} \\
\begin{leftwordgroup}{\texttt{CONF\_DONE}}
\bitbox{1}{P} & \bitbox{1}{0} & \bitbox{1}{1} & \bitbox{1}{F2} & \bitbox{1}{F1} & \bitbox{1}{U} & \bitbox{1}{I} & \bitbox{1}{C}
\bitbox{1}{P} & \colorbitbox{lightgray}{1}{0} & \colorbitbox{lightgray}{1}{1} & \bitbox{1}{F2} & \bitbox{1}{F1} & \bitbox{1}{U} & \bitbox{1}{I} & \bitbox{1}{C}
\end{leftwordgroup} \\
\bitheader[endianness=big]{0-7} \\
\begin{leftwordgroup}{\texttt{READY}}
\bitbox{1}{P} & \bitbox{1}{0} & \bitbox{1}{1} & \bitbox{1}{F2} & \bitbox{1}{F1} & \bitbox{3}{Rsvd}
\bitbox{1}{P} & \colorbitbox{lightgray}{1}{1} & \colorbitbox{lightgray}{1}{0} & \bitbox{1}{F2} & \bitbox{1}{F1} & \bitbox{3}{Rsvd}
\end{leftwordgroup} \\
\bitheader[endianness=big]{0-7} \\
\begin{leftwordgroup}{\texttt{UNDERRUN}}
\bitbox{1}{P} & \bitbox{1}{0} & \bitbox{1}{1} & \bitbox{1}{F2} & \bitbox{1}{F1} & \bitbox{3}{Rsvd}
\bitbox{1}{P} & \colorbitbox{lightgray}{1}{1} & \colorbitbox{lightgray}{1}{1} & \bitbox{1}{F2} & \bitbox{1}{F1} & \bitbox{3}{Rsvd}
\end{leftwordgroup} \\
\end{bytefield}
\let\bf@leftcurly=\{
\makeatother
\end{lrbox}
\begin{tabular}{lm{0.3\textwidth}}
\noindent\parbox[c]{0.56\textwidth}{
\usebox\bytefieldbox
}
&
\scriptsize
Legend:\vspace{-0.6em}
\begin{description}[labelindent=1.5em,itemsep=4pt,itemindent=0.5cm,parsep=0pt,style=sameline,font={\normalfont}]
\item[P] (even) Parity
\item[F1/2] Fault Detect 1 \& 2
\item[U] UART receive error
\item[I] ID mismatch
\item[C] CRC mismatch
\end{description}
\\
\end{tabular}
\begin{bytefield}[bitwidth=2em]{8}
\begin{bytefield}[rightcurly=.,bitwidth=2em]{8}
\bitheader[endianness=big]{0-7} \\
\begin{rightwordgroup}{2 fault patterns (e.g., for 3 FIUs) \\[.1em]
\footnotesize{FIU\#~$\frac{\text{Pattern\#}}{\text{Bit}}$}}
\bitbox{1}{2 $\frac{1}{1}$} & \bitbox{1}{2 $\frac{1}{0}$} & \bitbox{6}{Stuffing} \\
\bitbox{1}{1 $\frac{2}{0}$} & \bitbox{1}{1 $\frac{1}{2}$} & \bitbox{1}{1 $\frac{1}{1}$} & \bitbox{1}{1 $\frac{1}{0}$} & \bitbox{1}{2 $\frac{2}{2}$} & \bitbox{1}{2 $\frac{2}{1}$} & \bitbox{1}{2 $\frac{2}{0}$} & \bitbox{1}{2 $\frac{1}{2}$} \\
\bitbox{1}{0 $\frac{2}{2}$} & \bitbox{1}{0 $\frac{2}{1}$} & \bitbox{1}{0 $\frac{2}{0}$} & \bitbox{1}{0 $\frac{1}{2}$} & \bitbox{1}{0 $\frac{1}{1}$} & \bitbox{1}{0 $\frac{1}{0}$} & \bitbox{1}{1 $\frac{2}{2}$} & \bitbox{1}{1 $\frac{2}{1}$}\end{rightwordgroup} \\
\bitbox{8}{Duration $t_1$ [7:0]} \\
\bitbox{8}{\ldots} \\
\bitbox{8}{Duration $t_1$ [N-1:N-8]} \\
\bitbox{8}{Duration $t_2$ [7:0]} \\
\bitbox{8}{\ldots} \\
\bitbox{8}{Duration $t_2$ [N-1:N-8]} \\
\bitbox{1}{U} & \bitbox{4}{Reserved} & \bitbox{1}{R} & \bitbox{1}{XT} & \bitbox{1}{TE} \\
\bitbox{8}{ID [7:0]} \\
\bitbox{8}{ID [15:8]} \\
\bitbox{8}{CRC8 (CCITT)} \\
\begin{rightwordgroup}{\noindent\hspace{0.5em}\begin{minipage}{0.40\textwidth}2 fault patterns (e.g., for 3 FIUs) \\[.1em]
\footnotesize{FIU\#~$\frac{\text{Pattern\#}}{\text{Bit}}$}\end{minipage}}
\colorbitbox{LightYellow}{1}{2 $\frac{1}{1}$} & \colorbitbox{LightYellow}{1}{2 $\frac{1}{0}$} & \colorbitbox{LightGray!50!white}{6}{Stuffing} \\
\colorbitbox{LightCyan}{1}{1 $\frac{2}{0}$} & \colorbitbox{LightCyan}{1}{1 $\frac{1}{2}$} & \colorbitbox{LightCyan}{1}{1 $\frac{1}{1}$} & \colorbitbox{LightCyan}{1}{1 $\frac{1}{0}$} & \colorbitbox{LightYellow}{1}{2 $\frac{2}{2}$} & \colorbitbox{LightYellow}{1}{2 $\frac{2}{1}$} & \colorbitbox{LightYellow}{1}{2 $\frac{2}{0}$} & \colorbitbox{LightYellow}{1}{2 $\frac{1}{2}$} \\
\colorbitbox{MistyRose}{1}{0 $\frac{2}{2}$} & \colorbitbox{MistyRose}{1}{0 $\frac{2}{1}$} & \colorbitbox{MistyRose}{1}{0 $\frac{2}{0}$} & \colorbitbox{MistyRose}{1}{0 $\frac{1}{2}$} & \colorbitbox{MistyRose}{1}{0 $\frac{1}{1}$} & \colorbitbox{MistyRose}{1}{0 $\frac{1}{0}$} & \colorbitbox{LightCyan}{1}{1 $\frac{2}{2}$} & \colorbitbox{LightCyan}{1}{1 $\frac{2}{1}$}\end{rightwordgroup} \\
\colorbitbox{LightGreen!30!white}{8}{Duration $t_1$ [7:0]} \\
\colorbitbox{LightGreen!30!white}{8}{$\cdots$} \\
\colorbitbox{LightGreen!30!white}{8}{Duration $t_1$ [N-1:N-8]} \\
\colorbitbox{LightGreen!50!white}{8}{Duration $t_2$ [7:0]} \\
\colorbitbox{LightGreen!50!white}{8}{$\cdots$} \\
\colorbitbox{LightGreen!50!white}{8}{Duration $t_2$ [N-1:N-8]} \\
\begin{rightwordgroup}{%
\noindent\hspace{0.5em}\begin{minipage}{0.30\textwidth}
\scriptsize
\begin{description}[labelindent=0em,leftmargin=2.3em,style=sameline,itemsep=4pt,parsep=0pt,font={\normalfont}]
\item[TE] Trigger Enable
\item[XT] eXternal/$\overline{\textrm{internal}}$ Trigger
\item[R] Reset DUT after config
\item[U] Update status only (dryrun)
\end{description}
\end{minipage}
}
\bitbox{1}{U} & \bitbox{4}{Reserved} & \bitbox{1}{R} & \bitbox{1}{XT} & \bitbox{1}{TE}
\end{rightwordgroup} \\
\colorbitbox{LightCyan}{8}{ID [7:0]} \\
\colorbitbox{LightCyan}{8}{ID [15:8]} \\
\colorbitbox{MistyRose}{8}{CRC8 (CCITT)} \\
\end{bytefield}
......@@ -189,6 +189,13 @@
\usetikztiminglibrary{overlays}
\usepackage{bytefield}
%http://tex.stackexchange.com/a/302403/23277
\newcommand{\colorbitbox}[3]{%
\sbox0{\bitbox{#2}{#3}}%
\makebox[0pt][l]{\textcolor{#1}{\rule[-\dp0]{\wd0}{\ht0}}}%
\bitbox{#2}{#3}%
}
\DeclareMathDelimiter{\bsp}{\mathopen} {symbols}{"00}{symbols}{"00}
% Define global page properties %
......
......@@ -104,11 +104,11 @@
\node [document, below of=synth1] (orignetlist) {Original\\Netlist};
\node [ourtool, right of=synth1, node distance = 4cm] (setup) {\texttt{fiji\_setup.pl}};
\node [userdoc, above of=setup] (fireq) {FI\\Requirements};
\node [document, below of=setup] (ocfg) {FI\\Configuration};
\node [document, below of=setup] (ocfg) {FIJI\\Settings};
\node [ourtool, right of=setup, node distance = 4cm] (instrument) {\texttt{fiji\_instrument.pl}};
\node [document, below right of=instrument, node distance = 3cm] (vhdl) {VHDL\\Wrapper \& Config};
\node [document, below of=vhdl, node distance = 2cm] (modnetlist) {Modified\\Netlist};
\node [document, below of=modnetlist, node distance = 2cm] (icfg) {FI\\Configuration\\with ID};
\node [document, below of=modnetlist, node distance = 2cm] (icfg) {FIJI\\Settings\\with ID};
\node [block, right of=instrument, node distance = 6cm] (synth2) {Synthesis Tool};
\node [userproc, above of=synth2, node distance = 3.2cm] (adapt) {Adapt};
\node [document, above right of=synth2] (fijihdl) {FIJI HDL};
......@@ -148,8 +148,8 @@
\path [line] (vhdl.east) -| ($(synth2)+(-1.75,1.25)$) -| ($(synth2.north)-(0.33,0)$);
\path [line] (modnetlist.east) -| ($(synth2)+(-1.5,1)$) -| ($(synth2.north)-(0.66,0)$);
\path [line] (icfg.east) |- ($(dlcli)+(2,-8)$) |- ($(dlcli)+(0.5,2)$) -- ($(dlcli.north)+(0.5,0)$);
\path [line] ($(dlcli)+(0.5,2)$) -| ($(dlgui.north)+(0.5,0)$);
\path [line] (icfg.east) |- ($(dlcli)+(2,-8)$) |- ($(dlcli)+(0.25,2)$) -- ($(dlcli.north)+(0.25,0)$);
\path [line] ($(dlcli)+(0.25,2)$) -| ($(dlgui.north)+(0.25,0)$);
\path [line] (adapt.south) -- (synth2.north);
\path [line] (fijihdl.west) -| ($(synth2.north)+(0.33,0)$);
......@@ -163,8 +163,8 @@
\path [line] (dlcli) |- ($(dlcli)-(0,0.7)$) -- ($(fpga)+(0.2,1.6)$);
\path [line] (dlgui) |- ($(dlgui)-(0,0.7)$) -- ($(fpga)+(-0.2,1.6)$);
\path [line] ($(dlgui.south)-(0.5,0)$) |- ($(dlgui)-(0.5,1)$) -| (tstconf.south);
\path [line] (tstconf) -| (dlcli);
\path [line] (tstconf) -| (dlgui);
\path [line] (tstconf) -| ($(dlcli.north)-(0.25,0)$);
\path [line] (tstconf) -| ($(dlgui.north)-(0.25,0)$);
......
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