Added testcases to simulation

hw/sim/psl/fault_injection_controller.psl

@@ -186,4 +186,4 @@ vunit fic (fault_injection_controller(rtl)) {
 
     timer_completion:       assert always prop_timer_completion;
     timer_idle:             assert always prop_timer_idle;
-}
\ No newline at end of file
+}

hw/sim/sim_fault_injection_controller.do

@@ -79,6 +79,58 @@ for {set i $argc} {$i > 0} {incr i -1} {
     shift
 }
 
+# The following cases are simulated:
+#                             single_testcases/testcase_0.cfg                         C100         \
+#                               Initial config without errors & both timers 0
+#                             single_testcases/testcase_0_id.cfg                      C100         \
+#                               Config with ID error
+#                             single_testcases/testcase_0_crc.cfg                     C100         \
+#                               Config with CRC error
+#                             single_testcases/testcase_0_uart.cfg                    C100         \
+#                               Config with UART error
+#                             single_testcases/testcase_0_uart_id.cfg                 C100         \
+#                               Config with UART and CRC error
+#                             single_testcases/testcase_0_uart_crc.cfg                C100         \
+#                               Config with UART startbit error
+#                             single_testcases/testcase_0_uart_start.cfg              C100         \
+#                               Config with ID and CRC error
+#                             single_testcases/testcase_0_id_crc.cfg                  C100         \
+#                               Config with UART, ID, and CRC error
+#                             single_testcases/testcase_0_uart_id_crc.cfg             C100         \
+#                               Config with fault models in pattern 1 and pass_through in pattern 2
+#                             single_testcases/testcase_inj_noinj.cfg                 C100         \
+#                               Config with reset, fault models in pattern 1 and pass_through in pattern 2
+#                             single_testcases/testcase_inj_noinj_rst.cfg             C100         \
+#                               Config with ext_trigger, fault models in pattern 1 and pass_through in pattern 2
+#                             single_testcases/testcase_inj_noinj_trigger_ext.cfg     {C100 T1}    \
+#                               Config with ext_trigger + reset, fault models in pattern 1 and pass_through in pattern 2
+#                             single_testcases/testcase_inj_noinj_trigger_ext_rst.cfg {C100 T1}    \
+#                               Config with int_trigger, fault models in pattern 1 and pass_through in pattern 2
+#                             single_testcases/testcase_inj_noinj_trigger_int.cfg     {C100 I1}    \
+#                               Config with int_trigger + reset, fault models in pattern 1 and pass_through in pattern 2
+#                             single_testcases/testcase_inj_noinj_trigger_int_rst.cfg {C100 I1}    \
+#                               Config with fault models in pattern 1 and pass_through in pattern 2, long timer, underrun
+#                             single_testcases/testcase_inj_noinj_long_timer.cfg      C59000       \
+#                               Config with fault models in pattern 1 and pass_through in pattern 2, long timer
+#                             single_testcases/testcase_inj_noinj_long_timer.cfg      C32768       \
+#                               Config with fault models in pattern 1 and pass_through in pattern 2, DRY_RUN flag set
+#                             single_testcases/testcase_0_n.cfg                       C100         \
+#                               Config with fault models in pattern 1 and pass_through in pattern 2, long timer, underrun
+#                             single_testcases/testcase_inj_noinj_long_timer.cfg      C100000      \
+#                               Configs to force generation of 4 messages within a few (5) clock cycles -> Buffer Overflow, last message gets lost.
+#                             single_testcases/testcase_4msg_a.cfg                    C1           \
+#                             single_testcases/testcase_4msg_b.cfg                    C100         \
+#                               Configs to force replacing a UNDERRUN with a CONF_DONE at last chance
+#                               This is a tricky case: Actually, it's an UNDERRUN, because the next config
+#                               is applied by the current HW 1 clock cycle late, but we can't report it
+#                               because the UNDERRUN message is overwritten by a CONF_DONE message.
+#                             single_testcases/testcase_replace_underrun_a.cfg        C1           \
+#                             single_testcases/testcase_replace_underrun_b.cfg        C100         \
+#
+#    ATTENTION: Some of the testcases assume the current BAUD RATE and CLOCK FREQUENCY as default and
+#    may lead to different results when these values are changed!
+
+
 if {[llength $args] == 0} {
     set FIJI_ID 0x0123
     set args [list cfg_list {single_testcases/testcase_0.cfg                         C100         \
@@ -99,10 +151,14 @@ if {[llength $args] == 0} {
                              single_testcases/testcase_inj_noinj_long_timer.cfg      C59000       \
                              single_testcases/testcase_inj_noinj_long_timer.cfg      C32768       \
                              single_testcases/testcase_0_n.cfg                       C100         \
-                             single_testcases/testcase_inj_noinj_long_timer.cfg      C1           }\
+                             single_testcases/testcase_inj_noinj_long_timer.cfg      C100000      \
+                             single_testcases/testcase_4msg_a.cfg                    C1           \
+                             single_testcases/testcase_4msg_b.cfg                    C100         \
+                             single_testcases/testcase_replace_underrun_a.cfg        C1           \
+                             single_testcases/testcase_replace_underrun_b.cfg        C100         \
+                             }\
                     0x0123]
     set simtime "3 ms"
-
 }
 
 if { [make_test_file FIJI_ID DATA_FILE_NAME $CRC8_POLY $CRC8_INITIAL $args control] != 0} {
@@ -115,4 +171,4 @@ sim $DATA_FILE_NAME $FIJI_ID $CRC8_INITIAL $CRC8_POLY $LFSR_WIDTH $LFSR_SEED $LF
 
 if {$simtime != ""} {
     run $simtime
-}
\ No newline at end of file
+}

hw/tb/test_public_config_pkg.vhd

@@ -25,7 +25,6 @@
 --  Default public config package for testbenches
 --------------------------------------------------------------------------------
 
--- Automatically generated Thu May 21 11:00:13 2015
 library ieee;
     use ieee.std_logic_1164.all;
 
@@ -34,6 +33,12 @@ library work;
 
 package public_config_pkg is
 
+  ------------------------------------------------------------------------------
+  -- Attention: Some test cases require the exact c_frequency and c_baudrate
+  -- as set below and may lead to other results when these values are changed
+  -- i.e. different coverage
+  ------------------------------------------------------------------------------
+
   ------------------------------------------------------------------------------
   -- Design configuration
   ------------------------------------------------------------------------------