Commit 57cae241 authored by Stefan Tauner's avatar Stefan Tauner
Browse files

Refine to new interface

parent da1a2d8c
......@@ -552,7 +552,7 @@ sub instrument_net {
# If the driver is a pin of a (sub)cell, connect this pin to the intermediate net
$logger->debug("Connecting (output) pin \"" . $connection->cell->name . HIERSEP . $connection->name . "\" to intermediate net \"$net_name_tmp\"");
# FIXME: do concatenations really work? They are apparently split already by Verilog::perl but...
for my $netname (@{$connection->netnames}) {
for my $netname ($connection->netnames) {
if ($netname->{'netname'} eq $net->name) {
$netname->{'netname'} = $net_name_tmp; # FIXME: do we need to force a re-link (by deleting $connection->nets)?
# This net is a vector if the underlying net is a bus and we do not just select a single bit
......@@ -1085,7 +1085,7 @@ sub _get_net_connections {
foreach my $cell ($mod->cells) {
foreach my $pin ($cell->pins) {
my $bit_offset_total = 0;
foreach my $netname (@{$pin->netnames}) {
foreach my $netname ($pin->netnames) {
my $bit_offset_range = _offset_of_bit_in_range($bit, $netname->{'msb'}, $netname->{'lsb'});
if ($netname->{'netname'} eq $net_name && ($bit_offset_range != -1)) {
# Remember the bit's offset
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