Commit 57bf8504 authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

Added TMR VGA demo, supports zybo and de0

parent 58d5e813
### FIJI Demo Makefile
# Leads through a possible FIJI flow:
# 1. Synthesize original design to vqm netlist
# 2 generate/edit a fiji configuration file
# 3. generate an instrumented netlist + wrapper/pkg VHD files
# 4. lead through synplify project creation
# 5. lead through quartus project creation
# 6. P&R the modified netlist
# 7. Program FPGA with FIJI bitstream
# 8. execute FIJI test patterns (random, auto, manual)
## Select the used board by setting BOARD= as a commandline argument
## Select the used testcase by setting FIJI_PROJECT_NAME= as a commandline argumetn
# Environment setup
SHELL=/bin/bash
EDITOR?=nano
DBG?=no
BOARD?=zybo
PERLFLAGS=-I $(FIJI_SCRIPT_DIR)/FIJI -I $(FIJI_SCRIPT_DIR) -I $(FIJI_SCRIPT_DIR)/Log
# FIJI environment
FIJI_SCRIPT_DIR=../../../bin
FIJI_SETUP=$(FIJI_SCRIPT_DIR)/fiji_setup.pl
FIJI_INSTRUMENT=$(FIJI_SCRIPT_DIR)/fiji_instrument.pl
FIJI_EXECUTE=$(FIJI_SCRIPT_DIR)/fiji_ee.pl
FIJI_EXECUTE_GUI=$(FIJI_SCRIPT_DIR)/fiji_ee_gui.pl
FIJI_DIR=fiji
TOPLEVEL_MODULE=spriteflyer_top
FILE_PREFIX=tmr_vga_demo
FIJI_PORT=/dev/ttyUSB0
include boards/$(BOARD).mk
# Project directories and files
FIJI_PROJECT_DIR=$(FIJI_DIR)/$(FIJI_PROJECT_NAME)
FIJI_OUTPUT_DIR=$(FIJI_PROJECT_DIR)/fiji
MODIFIED_NETLIST_FILE=$(FIJI_OUTPUT_DIR)/$(FILE_PREFIX)_instrumented.$(NETLIST_SUFFIX)
FIJI_CFG_FILE=$(FIJI_OUTPUT_DIR)/fiji.cfg
TEST_FILE=$(FIJI_OUTPUT_DIR)/$(FIJI_PROJECT_NAME).tst
DOWNLOAD_CFG=$(FIJI_OUTPUT_DIR)/$(FILE_PREFIX)_download.cfg
ifneq ($(DBG),no)
PERLFLAGS+=-d:ptkdb
endif
# always provide opportunity to edit test and settings files
.PHONY: $(TEST_FILE)
# provide opportunity to edit fiji.cfg and then execute test file
all: setup-launch execute-gui
$(FIJI_CFG_FILE): setup-launch
$(ORIGINAL_NETLIST_FILE):
clear
@read -p "Press [Enter] after you synthesized the original netlist to $(ORIGINAL_NETLIST_FILE)..."
# launch the fiji settings editor GUI
setup-launch: $(ORIGINAL_NETLIST_FILE)
clear
@echo
@echo " FIJIFIJIFIJIFIJIFIJIFIJIFIJIFIJIFIJIFIJI"
@echo " FIJIFIJIFIJIFIJIF FIJIFIJIFIJIFIJIFIJI"
@echo " FIJIFIJIFIJIFIJ IFIJIFIJIFIJIFIJIFIJI"
@echo " FIJIF FI IJIFIJIFIJIFIJI"
@echo " FIJIFIJIFI JIFIJIFIJIFIJIFIJI"
@echo " FIJIFIJI FIJIFIJIFIJIFIJIFIJI"
@echo " FIJIFI I IFI IJIFIJIFIJIFIJIFIJI"
@echo " FIJIF JIFIJ JIFIJIFIJIFIJIFIJI"
@echo " FIJIFIJIFI IJIFIJI IFIJIFIJIFIJIFIJI"
@echo " FIJIFIJIF IJIFIJIFIJIFIJIFIJIFIJIFIJI"
@echo " FIJIFIJI FIJIFIJIFIJIFIJIFIJIFIJIFIJI"
@echo " FIJIFIJ FIJIF FIJIFIJIFIJI"
@echo " FIJIFI IFI Fault IFIJIFIJI"
@echo " FIJIF InJection FIJIFIJI"
@echo " FIJ Instrumenter IJIFIJI"
@echo " F IJI"
@echo " FIJIFIJIFIJIFIJIFIJIFIJIFIJIFIJIFIJIFIJI"
@echo
@echo "Press enter to edit the fiji configuration file or enter \"s\" to skip..."
@read skipedit ; \
if [ x"$${skipedit}" != x"s" ]; then \
perl $(PERLFLAGS) $(FIJI_SETUP) --settings-file=$(FIJI_CFG_FILE) --netlist-file=$(ORIGINAL_NETLIST_FILE) ; \
fi
# Generate the instrumented netlist and wrapper/config VHDL files
$(MODIFIED_NETLIST_FILE): $(ORIGINAL_NETLIST_FILE) $(FIJI_CFG_FILE)
@echo "Instrumenting for $(MODIFIED_NETLIST_FILE)"
perl $(PERLFLAGS) $(FIJI_INSTRUMENT) --fiji-settings-file=$(FIJI_CFG_FILE) \
--netlist-file=$(ORIGINAL_NETLIST_FILE) \
--file-prefix=$(FILE_PREFIX) \
--output_dir=$(FIJI_OUTPUT_DIR)
clear
# Open editor to modify test file
$(TEST_FILE):
@read -p "Press [Enter] to edit the test file..."
perl $(PERLFLAGS) $(FIJI_EXECUTE_GUI) -s $(FIJI_CFG_FILE) -t $(TEST_FILE)
# Prompt the user to execute the FPGA bitstream
# TODO: Automatization possible?
program-fpga: $(BITSTREAM_FILE)
@read -p "Press [Enter] after you programmed the FPGA..."
# Prompt the user to generate the new Synplify project and display instructions
# on-screen
# TODO: Automatization possible?
$(FIJI_SYNPLIFY_PROJECT):
@echo "Follow these instructions to generate the Synplify project $(FIJI_SYNPLIFY_PROJECT):"
@echo
@echo "0. Open terminal in $(FIJI_PROJECT_DIR)/synp"
@echo
@less $(FIJI_PROJECT_DIR)/synp/README
@echo
@read -p "Press [Enter] when you are ready..."
# Prompt the user to generate the new Quartus project and display instructions
# on-screen
# TODO: Automatization possible?
$(FIJI_PNR_PROJECT):
@echo "Follow these instructions to generate the Quartus project $(FIJI_PNR_PROJECT):"
@echo
@echo "0. Open terminal in $(FIJI_PROJECT_DIR)/$(FIJI_PNR_DIR)"
@echo
@less $(FIJI_PROJECT_DIR)/$(FIJI_PNR_DIR)/README
@echo
@read -p "Press [Enter] when you are ready..."
# Prompt the user to place&route the modified netlist + wrapper
# TODO: Automatization possible?
$(BITSTREAM_FILE): $(MODIFIED_NETLIST_FILE) $(FIJI_SYNPLIFY_PROJECT) $(FIJI_PNR_PROJECT)
@echo "Place & Route the modified netlist:"
@echo ' in Quartus: "Compile Design"'
@echo ' in Vivado: "Implement Design" and "Generate Bitstream"'
@echo
@read -p "Press [Enter] when you are ready..."
# Interactive test execution mode
execute-manual: $(BITSTREAM_FILE) $(TEST_FILE) program-fpga
perl $(PERLFLAGS) $(FIJI_EXECUTE) --mode=manual --settings=$(DOWNLOAD_CFG) --tests=$(TEST_FILE) --port=$(FIJI_PORT)
# Interactive test execution mode
# execute the tests in TEST_FILE
execute-auto: $(BITSTREAM_FILE) $(TEST_FILE) program-fpga
perl $(PERLFLAGS) $(FIJI_EXECUTE) --mode=auto --settings=$(DOWNLOAD_CFG) --tests=$(TEST_FILE) --port=$(FIJI_PORT)
# Random test execution mode
# execute random tests generated according the time and fault probability
# constraints
execute-random: $(BITSTREAM_FILE) $(TEST_FILE) program-fpga
perl $(PERLFLAGS) $(FIJI_EXECUTE) --mode=random --settings=$(DOWNLOAD_CFG) --tests=$(TEST_FILE) \
-a=200000 -A=1000000 \
-b=200000 -B=1000000 \
-0=0.19 \
-1=0.2 \
-d=0.2 \
-f=0.2 \
-o=0.2 --port=$(FIJI_PORT)
execute-gui: $(BITSTREAM_FILE) program-fpga
perl $(PERLFLAGS) $(FIJI_EXECUTE_GUI) --settings-file=$(DOWNLOAD_CFG) --tests-file=$(TEST_FILE)
For each board, a <Boardname>.mk file in this directory sets the
correct paths to the generated project directories and files.
Board-specific constraint files can also be placed here.
# Project settings
# Default project, if FIJI_PROJECT_NAME is not passed as make argument
FIJI_PROJECT_NAME?=de0_test_1
FIJI_PNR_DIR=quartus
NETLIST_SUFFIX=vqm
ORIGINAL_NETLIST_FILE=synp/de0/de0/spriteflyer_top.vqm
FIJI_SYNPLIFY_PROJECT=$(FIJI_PROJECT_NAME)/synp/$(TOPLEVEL_MODULE).prj
FIJI_PNR_PROJECT=$(FIJI_PROJECT_NAME)/$(FIJI_PNR_DIR)/$(FIJI_PROJECT_NAME).qpf
BITSTREAM_FILE=$(FIJI_PROJECT_DIR)/$(FIJI_PNR_DIR)/output_files/fiji_top.sof
set_location_assignment PIN_K22 -to s_blue_o[0]
set_location_assignment PIN_K21 -to s_blue_o[1]
set_location_assignment PIN_J22 -to s_blue_o[2]
set_location_assignment PIN_K18 -to s_blue_o[3]
set_location_assignment PIN_H22 -to s_green_o[0]
set_location_assignment PIN_J17 -to s_green_o[1]
set_location_assignment PIN_K17 -to s_green_o[2]
set_location_assignment PIN_J21 -to s_green_o[3]
set_location_assignment PIN_L21 -to s_hsync_o
set_location_assignment PIN_H19 -to s_red_o[0]
set_location_assignment PIN_H17 -to s_red_o[1]
set_location_assignment PIN_H20 -to s_red_o[2]
set_location_assignment PIN_H21 -to s_red_o[3]
set_location_assignment PIN_J6 -to s_tmr_en_i
set_location_assignment PIN_J1 -to s_ledg_o[0]
set_location_assignment PIN_J2 -to s_ledg_o[1]
set_location_assignment PIN_J3 -to s_ledg_o[2]
set_location_assignment PIN_H1 -to s_ledg_o[3]
set_location_assignment PIN_H2 -to s_reset_x_i
set_location_assignment PIN_L22 -to s_vsync_o
set_location_assignment PIN_G21 -to s_clk_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_blue_o[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_blue_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_blue_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_blue_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_clk_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_green_o[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_green_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_green_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_green_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_hsync_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_ledg_o[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_ledg_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_ledg_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_ledg_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_red_o[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_red_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_red_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_red_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_reset_x_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_tmr_en_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_vsync_o
set_instance_assignment -name SLEW_RATE 2 -to s_blue_o[3]
set_instance_assignment -name SLEW_RATE 2 -to s_blue_o[2]
set_instance_assignment -name SLEW_RATE 2 -to s_blue_o[1]
set_instance_assignment -name SLEW_RATE 2 -to s_blue_o[0]
set_instance_assignment -name SLEW_RATE 2 -to s_green_o[3]
set_instance_assignment -name SLEW_RATE 2 -to s_green_o[2]
set_instance_assignment -name SLEW_RATE 2 -to s_green_o[1]
set_instance_assignment -name SLEW_RATE 2 -to s_green_o[0]
set_instance_assignment -name SLEW_RATE 2 -to s_hsync_o
set_instance_assignment -name SLEW_RATE 2 -to s_ledg_o[3]
set_instance_assignment -name SLEW_RATE 2 -to s_ledg_o[2]
set_instance_assignment -name SLEW_RATE 2 -to s_ledg_o[1]
set_instance_assignment -name SLEW_RATE 2 -to s_ledg_o[0]
set_instance_assignment -name SLEW_RATE 2 -to s_red_o[3]
set_instance_assignment -name SLEW_RATE 2 -to s_red_o[2]
set_instance_assignment -name SLEW_RATE 2 -to s_red_o[1]
set_instance_assignment -name SLEW_RATE 2 -to s_red_o[0]
set_instance_assignment -name SLEW_RATE 2 -to s_vsync_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_blue_o[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_blue_o[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_blue_o[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_blue_o[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_green_o[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_green_o[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_green_o[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_green_o[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_hsync_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_ledg_o[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_ledg_o[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_ledg_o[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_ledg_o[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_red_o[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_red_o[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_red_o[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_red_o[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_vsync_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_clk_i
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_reset_x_i
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_tmr_en_i
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
\ No newline at end of file
set_property IOSTANDARD LVCMOS33 [get_ports {s_blue_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_blue_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_blue_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_blue_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_green_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_green_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_green_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_green_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_red_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_red_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_red_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_red_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports s_clk_i]
set_property IOSTANDARD LVCMOS33 [get_ports s_hsync_o]
set_property IOSTANDARD LVCMOS33 [get_ports s_vsync_o]
set_property SLEW FAST [get_ports s_vsync_o]
set_property SLEW FAST [get_ports s_hsync_o]
set_property SLEW FAST [get_ports {s_blue_o[3]}]
set_property SLEW FAST [get_ports {s_blue_o[2]}]
set_property SLEW FAST [get_ports {s_blue_o[1]}]
set_property SLEW FAST [get_ports {s_blue_o[0]}]
set_property SLEW FAST [get_ports {s_green_o[3]}]
set_property SLEW FAST [get_ports {s_green_o[2]}]
set_property SLEW FAST [get_ports {s_green_o[1]}]
set_property SLEW FAST [get_ports {s_green_o[0]}]
set_property SLEW FAST [get_ports {s_red_o[3]}]
set_property SLEW FAST [get_ports {s_red_o[2]}]
set_property SLEW FAST [get_ports {s_red_o[1]}]
set_property SLEW FAST [get_ports {s_red_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_blue_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_green_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_green_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_red_o[4]}]
set_property SLEW FAST [get_ports {s_red_o[4]}]
set_property SLEW FAST [get_ports {s_green_o[5]}]
set_property SLEW FAST [get_ports {s_green_o[4]}]
set_property SLEW FAST [get_ports {s_blue_o[4]}]
set_property PACKAGE_PIN G19 [get_ports {s_blue_o[4]}]
set_property PACKAGE_PIN J18 [get_ports {s_blue_o[3]}]
set_property PACKAGE_PIN K19 [get_ports {s_blue_o[2]}]
set_property PACKAGE_PIN M20 [get_ports {s_blue_o[1]}]
set_property PACKAGE_PIN P20 [get_ports {s_blue_o[0]}]
set_property PACKAGE_PIN F20 [get_ports {s_green_o[5]}]
set_property PACKAGE_PIN H20 [get_ports {s_green_o[4]}]
set_property PACKAGE_PIN J19 [get_ports {s_green_o[3]}]
set_property PACKAGE_PIN L19 [get_ports {s_green_o[2]}]
set_property PACKAGE_PIN N20 [get_ports {s_green_o[1]}]
set_property PACKAGE_PIN H18 [get_ports {s_green_o[0]}]
set_property PACKAGE_PIN F19 [get_ports {s_red_o[4]}]
set_property PACKAGE_PIN G20 [get_ports {s_red_o[3]}]
set_property PACKAGE_PIN J20 [get_ports {s_red_o[2]}]
set_property PACKAGE_PIN L20 [get_ports {s_red_o[1]}]
set_property PACKAGE_PIN M19 [get_ports {s_red_o[0]}]
set_property PACKAGE_PIN L16 [get_ports s_clk_i]
set_property PACKAGE_PIN P19 [get_ports s_hsync_o]
set_property PACKAGE_PIN R19 [get_ports s_vsync_o]
set_property IOSTANDARD LVCMOS33 [get_ports s_reset_x_i]
set_property IOSTANDARD LVCMOS33 [get_ports s_tmr_en_i]
set_property PACKAGE_PIN R18 [get_ports s_reset_x_i]
set_property PACKAGE_PIN G15 [get_ports s_tmr_en_i]
set_property PACKAGE_PIN M14 [get_ports {s_ledg_o[0]}]
set_property PACKAGE_PIN M15 [get_ports {s_ledg_o[1]}]
set_property PACKAGE_PIN G14 [get_ports {s_ledg_o[2]}]
set_property PACKAGE_PIN D18 [get_ports {s_ledg_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_ledg_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_ledg_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_ledg_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_ledg_o[0]}]
# Project settings
# Default project, if FIJI_PROJECT_NAME is not passed as make argument
FIJI_PROJECT_NAME?=zybo_test_1
FIJI_PNR_DIR=vivado
NETLIST_SUFFIX=vm
ORIGINAL_NETLIST_FILE=synp/zybo/zybo/spriteflyer_top.vm
FIJI_SYNPLIFY_PROJECT=$(FIJI_PROJECT_NAME)/synp/$(TOPLEVEL_MODULE).prj
FIJI_PNR_PROJECT=$(FIJI_PROJECT_NAME)/$(FIJI_PNR_DIR)/$(FIJI_PROJECT_NAME).xpr
BITSTREAM_FILE=$(FIJI_PROJECT_DIR)/$(FIJI_PNR_DIR)/$(FIJI_PROJECT_NAME).runs/impl_1/fiji_top.bit
Create new testcases by creating the following directory structure:
<Testcase Name>
├── <Testcase Name>/fiji
├── <Testcase Name>/synp
└── <Testcase Name>/vivado (if Xilinx device is used)
└── <Testcase Name>/quartus (if Altera device is used)
Copy the constraint files from de0_test_1/synp and de0_test_1/quartus
or zybo_test_1/synp and zybo_test_1/vivado and adapt them for your
testcase and board or create new constraint files.
; FIJI::ConfigSorted 0.1
; Thu Aug 18 12:25:31 2016
[CONSTS]
COMPLETION_SCRIPT=
FIJI_CFG=fiji.cfg
HALT_ON_CRC_ERROR=1
HALT_ON_FAULT_DETECT=1
HALT_ON_ID_ERROR=1
HALT_ON_UART_ERROR=1
HALT_ON_UNDERRUN=0
INITIAL_RESET=0
INITIAL_TRIGGER=NONE
MAX_DURATION_T1=10000000
MAX_DURATION_T2=10000000
MIN_DURATION_T1=1000000
MIN_DURATION_T2=1000000
MULTIFAULT=1
NUM_TESTS=1
PROB_DELAY=0.1
PROB_SEU=0.1
PROB_STUCK_AT_0=0.1
PROB_STUCK_AT_1=0.1
PROB_STUCK_OPEN=0.1
REPEAT=0
REPEAT_OFFSET=0
UART=/dev/ttyUSB0
[TEST0]
FIU_0_FAULT_1=NONE
FIU_0_FAULT_2=NONE
FIU_1_FAULT_1=NONE
FIU_1_FAULT_2=NONE
FIU_2_FAULT_1=NONE
FIU_2_FAULT_2=NONE
RESET_DUT_AFTER_CONFIG=0
TIMER_VALUE_1=1000000
TIMER_VALUE_2=1000000
TRIGGER=NONE
; FIJI::ConfigSorted 0.1
; Thu Aug 18 12:58:07 2016
[CONSTS]
BAUDRATE=115200
CFGS_PER_MSG=2
CLOCK_NET="spriteflyer_top/s_clk_c"
FAULT_DETECT_1_EN=1
FAULT_DETECT_1_INVERT=0
FAULT_DETECT_1_NAME="spriteflyer_top/s_blue_err"
FAULT_DETECT_2_EN=1
FAULT_DETECT_2_INVERT=0
FAULT_DETECT_2_NAME="spriteflyer_top/s_green_err"
FIU_CFG_BITS=3
FIU_NUM=3
FREQUENCY=50000000
IMPLEMENTATION_TOOL=ALTERA_QUARTUS
INSTRUMENTATION_LOG=fiji_instrument.log
LFSR_POLY=0x2d
LFSR_SEED=0xcafe
LFSR_WIDTH=16
OPTIMIZATIONS=ALLOW
OUTPUT_DIR=.
RESET_DUT_IN_ACTIVE=1
RESET_DUT_IN_DURATION=1
RESET_DUT_IN_EN=0
RESET_DUT_OUT_ACTIVE=0
RESET_DUT_OUT_EN=1
RESET_DUT_OUT_NAME="spriteflyer_top/s_reset_n_c"
RESET_EXT_ACTIVE=1
RESET_EXT_EN=0
RESET_EXT_IN_NAME=s_fiji_reset_i
RX_IN_NAME=s_fiji_rx_i
SYNTHESIS_TOOL=SYNPLIFY_PRO
TIMER_WIDTH=4
TRIGGER_DUT_ACTIVE=1
TRIGGER_DUT_EN=0
TRIGGER_DUT_NAME=""
TRIGGER_EXT_ACTIVE=0
TRIGGER_EXT_EN=1
TRIGGER_EXT_IN_NAME=s_fiji_trigger_ext_i
TX_OUT_NAME=s_fiji_tx_o
[FIU0]
DRIVER_PATH="\\spriteflyer_sprite_generate_tmr_partitions.0.i_sprite_0 /s_sprite_line_0_/q"
DRIVER_TYPE=PIN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x1
NET_NAME="spriteflyer_top/generate_tmr_partitions_0_i_sprite/s_sprite_line[0]"
[FIU1]
DRIVER_PATH="\\spriteflyer_sprite_generate_tmr_partitions.0.i_sprite_0 /s_x_state_Z/q"
DRIVER_TYPE=PIN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x2
NET_NAME="spriteflyer_top/generate_tmr_partitions_0_i_sprite/s_x_state"
[FIU2]
DRIVER_PATH="spriteflyer_top/generate_tmr_partitions_0_i_sprite/s_green_o"
DRIVER_TYPE=PIN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x4
NET_NAME="spriteflyer_top/s_green_tmr_partitions[3]"
1. Copy the following files into this directory:
../../../synp/de0/de0/spriteflyer_top_p_sprite_rom_s_sprit.hex
../../../synp/de0/de0/spriteflyer_top_p_sprite_rom_s_spritmif1.hex
../../../synp/de0/de0/spriteflyer_top_p_sprite_rom_s_spritmif2.hex
2. Create a new project named 'de0_test_1.qpf'
Set Cyclone III - EP3C16-F484-C6 as device
3. Add the following files to the project
../synp/de0/spriteflyer_top.vqm
../fiji/tmr_vga_demo_constraints.quartus.qsf
./fiji_top.sdc
4. Import the assignments from
../../../boards/pins_de0.qsf
./fiji_pins.qsf
The clock and pin constraints have already been entered for this demo.
In a 'real' project, you would have to manually enter them in Quartus.
5. Perform 'Analysis and Synthesis'
6. Check the imported pin assignments in the Pin Planner
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.0 Build 156 04/24/2013 SJ Full Version
# Date created = 12:32:31 August 18, 2016
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "12:32:31 August 18, 2016"
# Revisions
PROJECT_REVISION = "fiji_top"
set_location_assignment PIN_K22 -to s_blue_o[0]
set_location_assignment PIN_K21 -to s_blue_o[1]
set_location_assignment PIN_J22 -to s_blue_o[2]
set_location_assignment PIN_K18 -to s_blue_o[3]
set_location_assignment PIN_H22 -to s_green_o[0]
set_location_assignment PIN_J17 -to s_green_o[1]
set_location_assignment PIN_K17 -to s_green_o[2]
set_location_assignment PIN_J21 -to s_green_o[3]
set_location_assignment PIN_L21 -to s_hsync_o
set_location_assignment PIN_H19 -to s_red_o[0]
set_location_assignment PIN_H17 -to s_red_o[1]
set_location_assignment PIN_H20 -to s_red_o[2]
set_location_assignment PIN_H21 -to s_red_o[3]
set_location_assignment PIN_J6 -to s_tmr_en_i
set_location_assignment PIN_J1 -to s_ledg_o[0]
set_location_assignment PIN_J2 -to s_ledg_o[1]
set_location_assignment PIN_J3 -to s_ledg_o[2]
set_location_assignment PIN_H1 -to s_ledg_o[3]
set_location_assignment PIN_H2 -to s_reset_x_i
set_location_assignment PIN_L22 -to s_vsync_o
set_location_assignment PIN_G21 -to s_clk_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_blue_o[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_blue_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_blue_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_blue_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_clk_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_green_o[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_green_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_green_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_green_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_hsync_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_ledg_o[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_ledg_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_ledg_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_ledg_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_red_o[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_red_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_red_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_red_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_reset_x_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_tmr_en_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_vsync_o
set_instance_assignment -name SLEW_RATE 2 -to s_blue_o[3]
set_instance_assignment -name SLEW_RATE 2 -to s_blue_o[2]
set_instance_assignment -name SLEW_RATE 2 -to s_blue_o[1]
set_instance_assignment -name SLEW_RATE 2 -to s_blue_o[0]
set_instance_assignment -name SLEW_RATE 2 -to s_green_o[3]
set_instance_assignment -name SLEW_RATE 2 -to s_green_o[2]
set_instance_assignment -name SLEW_RATE 2 -to s_green_o[1]
set_instance_assignment -name SLEW_RATE 2 -to s_green_o[0]
set_instance_assignment -name SLEW_RATE 2 -to s_hsync_o
set_instance_assignment -name SLEW_RATE 2 -to s_ledg_o[3]
set_instance_assignment -name SLEW_RATE 2 -to s_ledg_o[2]
set_instance_assignment -name SLEW_RATE 2 -to s_ledg_o[1]
set_instance_assignment -name SLEW_RATE 2 -to s_ledg_o[0]
set_instance_assignment -name SLEW_RATE 2 -to s_red_o[3]
set_instance_assignment -name SLEW_RATE 2 -to s_red_o[2]
set_instance_assignment -name SLEW_RATE 2 -to s_red_o[1]
set_instance_assignment -name SLEW_RATE 2 -to s_red_o[0]
set_instance_assignment -name SLEW_RATE 2 -to s_vsync_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_blue_o[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_blue_o[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_blue_o[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_blue_o[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_green_o[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_green_o[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_green_o[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_green_o[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_hsync_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_ledg_o[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_ledg_o[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_ledg_o[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_ledg_o[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_red_o[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_red_o[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_red_o[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_red_o[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_vsync_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_clk_i
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_reset_x_i
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_tmr_en_i
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_location_assignment PIN_G3 -to s_fiji_trigger_ext_i
set_location_assignment PIN_V6 -to s_fiji_tx_o
set_location_assignment PIN_V7 -to s_fiji_rx_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_fiji_rx_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_fiji_trigger_ext_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_fiji_tx_o