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vecs
FIJI Public
Commits
577056ce
Commit
577056ce
authored
Apr 13, 2017
by
Stefan Tauner
Browse files
Unify Zybo Synplify project with others
parent
c01d9f0a
Changes
1
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docs/demos/tmr_vga/synp/zybo/spriteflyer_top.prj
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577056ce
#-- Synopsys, Inc.
#-- Version
I
-201
3
.09-SP
1
#-- Version
J
-201
4
.09-SP
2
#project files
add_file -vhdl -lib work "../../rtl/spriteflyer_clkgen_.vhd"
...
...
@@ -8,7 +8,7 @@ add_file -vhdl -lib work "../../rtl/spriteflyer_pkg.vhd"
add_file -vhdl -lib work "../../rtl/spriteflyer_sprite_rtl.vhd"
add_file -vhdl -lib work "../../rtl/spriteflyer_top_rtl.vhd"
add_file -vhdl -lib work "../../rtl/spriteflyer_vga_rtl.vhd"
add_file -fpga_constraint "
./
spriteflyer_top.fdc"
add_file -fpga_constraint "spriteflyer_top.fdc"
add_file -vhdl -lib work "../../rtl/spriteflyer_input_sync_debounce.vhd"
add_file -vhdl -lib work "../../rtl/spriteflyer_voter_rtl.vhd"
...
...
@@ -80,5 +80,5 @@ set_option -auto_infer_blackbox 0
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "
.
/spriteflyer_top.vm"
project -result_file "
zybo
/spriteflyer_top.vm"
impl -active "zybo"
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