Unify Zybo Synplify project with others

docs/demos/tmr_vga/synp/zybo/spriteflyer_top.prj

 #--  Synopsys, Inc.
-#--  Version I-2013.09-SP1 
+#--  Version J-2014.09-SP2
 
 #project files
 add_file -vhdl -lib work "../../rtl/spriteflyer_clkgen_.vhd"
@@ -8,7 +8,7 @@ add_file -vhdl -lib work "../../rtl/spriteflyer_pkg.vhd"
 add_file -vhdl -lib work "../../rtl/spriteflyer_sprite_rtl.vhd"
 add_file -vhdl -lib work "../../rtl/spriteflyer_top_rtl.vhd"
 add_file -vhdl -lib work "../../rtl/spriteflyer_vga_rtl.vhd"
-add_file -fpga_constraint "./spriteflyer_top.fdc"
+add_file -fpga_constraint "spriteflyer_top.fdc"
 add_file -vhdl -lib work "../../rtl/spriteflyer_input_sync_debounce.vhd"
 add_file -vhdl -lib work "../../rtl/spriteflyer_voter_rtl.vhd"
 
@@ -80,5 +80,5 @@ set_option -auto_infer_blackbox 0
 set_option -write_apr_constraint 1
 
 #set result format/file last
-project -result_file "./spriteflyer_top.vm"
+project -result_file "zybo/spriteflyer_top.vm"
 impl -active "zybo"