Commit 5076a062 authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

Demos updated, small fix for VHDL wrapper generation

parent d2619aae
......@@ -299,8 +299,10 @@ sub export_as_vhd_fiji_architecture {
my $fiu_width = $design_ref->{'FIU_NUM'}-1;
my $lfsr_width_multiple_of_4 = ceil($design_ref->{'LFSR_WIDTH'}/4)*4-1;
my $lfsr_seed_hex = sprintf("%X",$design_ref->{'LFSR_SEED'});
my $lfsr_poly_hex = sprintf("%X",$design_ref->{'LFSR_POLY'});
my $lfsr_fmt = "\%0".ceil($design_ref->{'LFSR_WIDTH'}/4)."X";
print "============== $lfsr_fmt =================";
my $lfsr_seed_hex = sprintf($lfsr_fmt,$design_ref->{'LFSR_SEED'});
my $lfsr_poly_hex = sprintf($lfsr_fmt,$design_ref->{'LFSR_POLY'});
my $vhdl=<<"END_HDR";
------------------------------------------------------------------------
......
......@@ -19,5 +19,5 @@ module top (i,o);
mod inst2 (.i(i),.o(a));
assign u = {b};
assign bus2 = {bus1[15:7],1'b1,bus[5:0]};
assign bus2 = {bus1[15:7],1'b1,bus1[5:0]};
endmodule
\ No newline at end of file
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment