Commit 4b09ce57 authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
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Extended userguide

parent c810867a
%Silence bibtex error \cite{adams2007hitchhiker}
The Fault InJection Instrumenter (FIJI) suite provides a tool flow for
performing fault injection tests on chip designs in an FPGA-based environment.
In contrast to fault injection tests by modification of the RTL source,
FIJI targets the already synthesized design at the FPGA primitive level (e.g.,
LUTs, Flip-Flops, and the nets connecting them). Compared to fault injection
carried out with the help of partial reconfiguration, FIJI is relatively
technology-independent as no knowledge about the bitstream format and
the mapping to configuration frames within the FPGA device is required.
An overview of the FIJI tool flow is shown in Figure~\ref{fig:fijiflow}.
FIJI works by instrumenting a given netlist of a design under test with
fault injection logic according to a predefined fault injection configuration.
A parametrized Fault Injection Controller (FIC) hardware module is added outside
of the original design. The generation of the fault injection configuration
and the parametrization of the FIC is aided by the graphical user interface
provided by the \textit{FIJI Setup} tool, but can also be performed manually
or by a script, as this information is stored in text files in an INI-like
Instrumentation is done by the \textit{FIJI Instrument} tool. This tool
modifies the original netlist, and generates wrapper and configuration
packages in VHDL.
The user is then required to perform synthesis and place~\&~route of the
modified design and download the generated bitstream to the target hardware.
Test execution is facilitated by the \textit{FIJI Download} and
\textit{FIJI Download GUI} tools. These tools communicate with the FIC
over a standard (TTL-)serial interface, and instruct the fault injection
logic which tests to perform. Both of these tools support the execution of
manually specified tests, execution of test sequences, and randomly generated
test sequences.
Figure \ref{fig:fijioverview} provides an overview of the components
present in the host (PC) and the target hardware to facilitate fault
injection tests.
\caption{FIJI Overview}
\ No newline at end of file
All FIJI tools are written in Perl.
The following data is used as an input to FIJI:
\item The netlist to be subjected to fault injection.
Only Verilog-based netlists are supported, such as Altera's
Verilog Quartus Mapping (VQM) format, and Xilinx's Verilog
Mapping (VM) format.
\item Meta-information about the design (e.g., clock frequency)
\item The desired fault injection configuration (which faults on which nets)
\item The desired capabilities of the Fault Injection Controller (e.g., communication data rate, timer sizes)
\section{Installation \& Setup}
The prerequesites for running the \textit{FIJI} fault injection toolflow are
listed in Table~\ref{tab:prerequesites} alongside the version FIJI was
The prerequisites for running the \textit{FIJI} fault injection toolflow are
listed in Table~\ref{tab:prerequisites} alongside the version FIJI was
tested with. This does not include the Perl modules which need to be installed,
which can be found in Table~\ref{tab:perlmod}.
\caption{Software prerequesites for FIJI}
\caption{Software prerequisites for FIJI}
......@@ -227,8 +227,8 @@ can be seen in Figure~\ref{fig:download_gui}:
In \textit{Sequence Mode}, \textit{FIJI Download GUI} provides the
possibiltiy to edit a sequence of fault patterns to be downloaded one
In \textit{Sequence} mode, \textit{FIJI Download GUI} provides the
possibility to edit a sequence of fault patterns to be downloaded one
after another. In the \textit{Main Area} of the sequence mode tab
an overview of the currently configured sequence of test patterns
is displayed. Only the durations are displayed, the configured faults
......@@ -258,18 +258,35 @@ test is done or failed.
Figure~\ref{fig:manual_download_gui} shows the \textit{Main Area} with
\textit{Manual} mode selected. Here, the parameters of a single fault
configuration can be entered. By clicking the \textit{Start} button with
manual mode selected, the currently entered configuration is sent to
the fault injection logic where it is immediately activated when the
logic is ready.
As can also be seen in the Figure, the
hardware configuration information from the \textit{FIJI Settings} file
is incorporated in this view. In the hardware configuration for loaded
in the screenshot, the FIJI-to-DUT reset feature was turned off, and
\textit{FIJI Download GUI} notifies the user by graying-out the respective
\caption{FIJI Download Tool: Manual Mode}
The GUI elements for configuring the \textit{Random} test mode can be
seen in Figure~\ref{fig:random_download_gui}.
\caption{FIJI Download Tool: Random Mode}
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......@@ -151,8 +151,8 @@ user.
\item Download the FPGA bitstream via Quartus Downloader
\item \begin{verbatim}
$ perl mc8051_demo/fiji_test_1/fiji_demo_download.cfg \
$ perl -s mc8051_demo/fiji_test_1/fiji_demo_download.cfg \
-t mc8051_demo/fiji_test_1/fiji_demo_test.tst
\item Execute tests:
\begin {itemize}
\section{LFSR polynomials}
Table~\ref{tab:lfsrtable} provides \textit{maximum} polynomials for LFSRs
with widths between 2 and 64 bits ready to be used in a \textit{FIJI Settings}
An LFSR implemented using a maximal polynomial
provides a sequence with $2^{N}-1$ states where $N$ is the widths of the shift register.
It visits all possible bit vectors of length $N$ except all-zeroes.
\caption{Maximal period LFSR polynomials for lengths 2-64 \cite{tableLFSR}}
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