Commit 4944936d authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
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Basys3 VGA Demo

parent fba8bd36
# Project settings
# Default project, if FIJI_PROJECT_NAME is not passed as make argument
FIJI_PROJECT_NAME?=basys3_test_1
FIJI_PNR_DIR=vivado
NETLIST_SUFFIX=vm
ORIGINAL_NETLIST_FILE=synp/basys3/basys3/spriteflyer_top.vm
FIJI_SYNPLIFY_PROJECT=$(FIJI_PROJECT_NAME)/synp/$(TOPLEVEL_MODULE).prj
FIJI_PNR_PROJECT=$(FIJI_PROJECT_NAME)/$(FIJI_PNR_DIR)/$(FIJI_PROJECT_NAME).xpr
BITSTREAM_FILE=$(FIJI_PROJECT_DIR)/$(FIJI_PNR_DIR)/$(FIJI_PROJECT_NAME).runs/impl_1/fiji_top.bit
set_property IOSTANDARD LVCMOS33 [get_ports {s_blue_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_blue_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_blue_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_blue_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_green_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_green_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_green_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_green_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_red_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_red_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_red_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_red_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports s_clk_i]
set_property IOSTANDARD LVCMOS33 [get_ports s_hsync_o]
set_property IOSTANDARD LVCMOS33 [get_ports s_vsync_o]
set_property SLEW FAST [get_ports s_vsync_o]
set_property SLEW FAST [get_ports s_hsync_o]
set_property SLEW FAST [get_ports {s_blue_o[3]}]
set_property SLEW FAST [get_ports {s_blue_o[2]}]
set_property SLEW FAST [get_ports {s_blue_o[1]}]
set_property SLEW FAST [get_ports {s_blue_o[0]}]
set_property SLEW FAST [get_ports {s_green_o[3]}]
set_property SLEW FAST [get_ports {s_green_o[2]}]
set_property SLEW FAST [get_ports {s_green_o[1]}]
set_property SLEW FAST [get_ports {s_green_o[0]}]
set_property SLEW FAST [get_ports {s_red_o[3]}]
set_property SLEW FAST [get_ports {s_red_o[2]}]
set_property SLEW FAST [get_ports {s_red_o[1]}]
set_property SLEW FAST [get_ports {s_red_o[0]}]
set_property PACKAGE_PIN J18 [get_ports {s_blue_o[3]}]
set_property PACKAGE_PIN K18 [get_ports {s_blue_o[2]}]
set_property PACKAGE_PIN L18 [get_ports {s_blue_o[1]}]
set_property PACKAGE_PIN N18 [get_ports {s_blue_o[0]}]
set_property PACKAGE_PIN D17 [get_ports {s_green_o[3]}]
set_property PACKAGE_PIN G17 [get_ports {s_green_o[2]}]
set_property PACKAGE_PIN H17 [get_ports {s_green_o[1]}]
set_property PACKAGE_PIN J17 [get_ports {s_green_o[0]}]
set_property PACKAGE_PIN N19 [get_ports {s_red_o[3]}]
set_property PACKAGE_PIN J19 [get_ports {s_red_o[2]}]
set_property PACKAGE_PIN H19 [get_ports {s_red_o[1]}]
set_property PACKAGE_PIN G19 [get_ports {s_red_o[0]}]
set_property PACKAGE_PIN W5 [get_ports s_clk_i]
set_property PACKAGE_PIN P19 [get_ports s_hsync_o]
set_property PACKAGE_PIN R19 [get_ports s_vsync_o]
set_property IOSTANDARD LVCMOS33 [get_ports s_reset_x_i]
set_property IOSTANDARD LVCMOS33 [get_ports s_tmr_en_i]
set_property PACKAGE_PIN U18 [get_ports s_reset_x_i]
set_property PACKAGE_PIN V17 [get_ports s_tmr_en_i]
set_property PACKAGE_PIN U16 [get_ports {s_ledg_o[0]}]
set_property PACKAGE_PIN E19 [get_ports {s_ledg_o[1]}]
set_property PACKAGE_PIN U19 [get_ports {s_ledg_o[2]}]
set_property PACKAGE_PIN V19 [get_ports {s_ledg_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_ledg_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_ledg_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_ledg_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s_ledg_o[0]}]
1. Create a new Synplify project file named 'spriteflyer_top.prj'
2. Open the project
3. Rename the default implementation to 'basys3' and enter the following settings:
Device: Xilinx Artix xc7a35t-cpg236
Use Vivado: YES
Output Format: VM
Output Filename: spriteflyer_top.vm
Verilog toplevel module: fiji_top
4. Add the following files to the project:
../fiji/tmr_vga_demo_instrumented.vqm
../fiji/tmr_vga_demo_config_pkg.vhd
../fiji/tmr_vga_demo_wrapper.vhd
../fiji/tmr_vga_demo_constraints.synplify.fdc
<FIJI PUBLIC ROOT>/hw/rtl/*.vhd
./spriteflyer_top.fdc
The constraints have already been entered for this demo.
In a 'real' flow, they have to be manually transferred from
the original Synplify project
###==== BEGIN Header
# Synopsys, Inc. constraint file
# /home/fibich/git/vecs/fiji/fiji_public/docs/demos/tmr_vga/fiji/basys3_test_1/synp/spriteflyer_top.fdc
# Written on Tue Apr 11 12:35:58 2017
# by Synplify Pro, J-2014.09-SP2 FDC Constraint Editor
# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
# These sections are generated from SCOPE spreadsheet tabs.
###==== END Header
###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
###==== END Collections
###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
create_clock {p:s_clk_i} -period {10}
###==== END Clocks
###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
###==== END "Generated Clocks"
###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
###==== END Inputs/Outputs
###==== BEGIN Registers - (Populated from tab in SCOPE, do not edit)
###==== END Registers
###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
###==== END "Delay Paths"
###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
###==== END Attributes
###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
###==== END "I/O Standards"
###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
###==== END "Compile Points"
#-- Synopsys, Inc.
#-- Version J-2014.09-SP2
#-- Project file /home/fibich/git/vecs/fiji/fiji_public/docs/demos/tmr_vga/fiji/basys3_test_1/synp/spriteflyer_top.prj
#project files
add_file -fpga_constraint "spriteflyer_top.fdc"
add_file -vhdl -lib work "../fiji/tmr_vga_demo_config_pkg.vhd"
add_file -vhdl -lib work "../fiji/tmr_vga_demo_wrapper.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_controller_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_controller_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_controller_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_top_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_top_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_top_struc.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_tx_buffer_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_tx_buffer_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_tx_buffer_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_uart_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_uart_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_uart_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_unit_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_unit_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_unit_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_selection_type_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/private_config_pkg.vhd"
add_file -structver "../fiji/tmr_vga_demo_instrumented.vm"
add_file -fpga_constraint "../fiji/tmr_vga_demo_constraints.synplify.fdc"
#implementation: "basys3"
impl -add basys3 -type fpga
#
#implementation attributes
set_option -vlog_std sysv
set_option -project_relative_includes 1
#par_1 attributes
set_option -job par_1 -add par
#device options
set_option -technology Artix7
set_option -part XC7A35T
set_option -package CPG236
set_option -speed_grade -1
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
# mapper_options
set_option -frequency auto
set_option -write_verilog 1
set_option -write_vhdl 0
set_option -srs_instrumentation 1
# xilinx_options
set_option -RWCheckOnRam 1
# Xilinx Virtex2
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
# Xilinx Artix7
set_option -use_vivado 1
set_option -enable_prepacking 1
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "basys3/spriteflyer_top.vm"
impl -active "basys3"
1. Create a new Vivado post-synthesis project in the 'vivado' directory named 'basys3_test_1.xpr'
Add Source:
../synp/basys3/spriteflyer_top.vm as source
Add Constraints files:
../fiji/tmr_vga_demo_constraints.vivado.xdc
../../../boards/pins_basys3.xdc
./pins_fiji.xdc
./clock.xdc
The pin and clock constraints have already been added in this demo.
In a 'real' flow, these would have to be manually transferred or
entered.
Set xc7a35tcpg236-1 as device
Set fiji_top as toplevel module
2. Check pin and clock constraints
3. Run implementation and generate bitstream
create_clock -period 10.000 -name s_clk_i -waveform {0.000 5.000} [get_ports -filter { NAME =~ "*clk*" && DIRECTION == "IN" }]
set_property IOSTANDARD LVCMOS33 [get_ports s_fiji_rx_i]
set_property IOSTANDARD LVCMOS33 [get_ports s_fiji_tx_o]
set_property SLEW FAST [get_ports s_fiji_tx_o]
set_property PACKAGE_PIN B18 [get_ports s_fiji_rx_i]
set_property PACKAGE_PIN A18 [get_ports s_fiji_tx_o]
set_property PACKAGE_PIN T18 [get_ports s_fiji_trig_ext_i]
set_property IOSTANDARD LVCMOS33 [get_ports s_fiji_trig_ext_i]
This diff is collapsed.
###==== BEGIN Header
# Synopsys, Inc. constraint file
# /home/fibich/git/vecs/fiji/fiji_public/docs/demos/tmr_vga/synp/basys3/spriteflyer_top.fdc
# Written on Tue Apr 11 11:22:05 2017
# by Synplify Pro, J-2014.09-SP2 FDC Constraint Editor
# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
# These sections are generated from SCOPE spreadsheet tabs.
###==== END Header
###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
###==== END Collections
###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
create_clock {p:s_clk_i} -period {10}
###==== END Clocks
###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
###==== END "Generated Clocks"
###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
###==== END Inputs/Outputs
###==== BEGIN Registers - (Populated from tab in SCOPE, do not edit)
###==== END Registers
###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
###==== END "Delay Paths"
###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
define_global_attribute {syn_hier} {fixed}
###==== END Attributes
###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
###==== END "I/O Standards"
###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
###==== END "Compile Points"
#-- Synopsys, Inc.
#-- Version J-2014.09-SP2
#-- Project file /home/fibich/git/vecs/fiji/fiji_public/docs/demos/tmr_vga/synp/basys3/spriteflyer_top.prj
#project files
add_file -vhdl -lib work "../../rtl/spriteflyer_clkgen_.vhd"
add_file -vhdl -lib work "../../rtl/spriteflyer_pkg.vhd"
add_file -vhdl -lib work "../../rtl/spriteflyer_sprite_rtl.vhd"
add_file -vhdl -lib work "../../rtl/spriteflyer_top_rtl.vhd"
add_file -vhdl -lib work "../../rtl/spriteflyer_vga_rtl.vhd"
add_file -fpga_constraint "spriteflyer_top.fdc"
add_file -vhdl -lib work "../../rtl/spriteflyer_input_sync_debounce.vhd"
add_file -vhdl -lib work "../../rtl/spriteflyer_voter_rtl.vhd"
add_file -vhdl -lib work "../../rtl/spriteflyer_clkgen_basys3.vhd"
#implementation: "basys3"
impl -add basys3 -type fpga
#
#implementation parameter settings
set_option -hdl_param -set G_CLK_FREQUENCY 100000000
#device options
set_option -technology Artix7
set_option -part XC7A35T
set_option -package CPG236
set_option -speed_grade -1
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "work.spriteflyer_top.rtl"
# mapper_options
set_option -frequency 1.000000
set_option -write_verilog 1
set_option -write_vhdl 0
set_option -srs_instrumentation 1
# xilinx_options
set_option -RWCheckOnRam 1
# Xilinx Virtex2
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
# Xilinx Artix7
set_option -use_vivado 1
set_option -enable_prepacking 1
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "basys3/spriteflyer_top.vm"
impl -active "basys3"
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