Commit 49182e2d authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

Moved wrapper and package VHDL generation code to VHDL.pm

todo: check if generated VHDL compiles and contains all necessary constants and assignments
todo: documentation
todo: beautify default assignments ($FIJI_DEFAULTS)
parent 74923f67
This diff is collapsed.
; Config::Simple 4.58
; Mon May 4 16:02:25 2015
; Thu May 28 16:06:37 2015
[FIU0]
[FIU1]
FAULT_MODEL=RUNTIME
NET_NAME=a
LFSR_MASK=0x0
FAULT_MODEL=RUNTIME
[FIU1]
[FIU0]
FAULT_MODEL=RUNTIME
NET_NAME=a
LFSR_MASK=0x0
FAULT_MODEL=RUNTIME
[CONSTS]
TRIGGER_EXT_ACTIVE=1
TIMER_WIDTH=32
LFSR_WIDTH=16
CFGS_PER_MSG=2
TRIGGER_DUT_NAME=bb
RESET_DUT_IN_ACTIVE=1
RESET_DUT_IN_EN=0
TRIGGER_DUT_ACTIVE=1
TRIGGER_EXT_EN=0
LFSR_POLY=0x2d
BAUDRATE=115200
FREQUENCY=20000000
FIU_NUM=2
RESET_EXT_EN=0
TIMER_WIDTH=32
RESET_DUT_OUT_EN=0
CFGS_PER_MSG=2
RESET_DUT_IN_DURATION=4
TRIGGER_DUT_EN=0
LFSR_SEED=0xcafe
CLOCK_NET=clk
RESET_DUT_IN_NAME=bla
FIU_CFG_BITS=3
RESET_DUT_IN_EN=0
ID=0x0123
FREQUENCY=20000000
ID=0x123
RESET_DUT_OUT_NAME=bla
RESET_EXT_ACTIVE=1
RESET_DUT_OUT_ACTIVE=1
LFSR_SEED=0xcafe
FIU_NUM=2
LFSR_POLY=0x2d
BAUDRATE=115200
RESET_DUT_OUT_EN=0
## @file
use strict;
use warnings;
use Log::Log4perl qw(get_logger);
use FIJI::Connection;
use FIJI::Settings;
sub test_fi_uart {
my ($port, $payload_ref, $t1_duration, $t2_duration, $trigger_en, $trigger_ext, $reset, $fiji_consts) = @_;
# my @payload = map hex($_), $cfg_str =~ /(..)/g; # TODO: how to do this with unpack?
my %config = (
payload => $payload_ref,
t1_duration => $t1_duration,
t2_duration => $t2_duration,
trigger_en => $trigger_en,
trigger_ext => $trigger_ext,
reset => $reset,
consts => $fiji_consts,
);
$port->send_config(\%config, 1000, 0, 1);
}
sub main {
my @ARGV = @_;
my $logger = get_logger();
my $name = $0;
$name =~ s/\.p[lm]//;
my $cfgname = $name . ".cfg";
$logger->debug("=== Starting new execution of $name ===");
$logger->debug(sprintf("%d argument(s)%s", scalar(@_), scalar(@_) > 0 ? ": @_" : ""));
my $fiji_settings = FIJI::Settings->new('download', $ARGV[0]);
if (!ref($fiji_settings)) {
printf($fiji_settings . " Aborting.\n");
return 1;
}
my $fiji_consts = $fiji_settings->{'design'};
my $fius = $fiji_settings->{'FIUs'};
my $lfsr_fmt = sprintf("X\"%%0%dx\"",$fiji_consts->{'LFSR_WIDTH'}/4);
my @fiu_configs = ();
for (my $i = 0; $i < $fiji_consts->{'FIU_NUM'}; $i++) {
my $lfsr_mask = sprintf("$lfsr_fmt",@{$fius}[$i]->{'FIU_LFSR_MASK'});
my $str =<<"END_FIU";
$i => (
fault_model => @{$fius}[$i]->{'FIU_MODEL'},
lfsr_mask => $lfsr_mask
)
END_FIU
push @fiu_configs,$str;
}
my $lfsr_poly_string = sprintf($lfsr_fmt,$fiji_consts->{'LFSR_POLY'});
my $lfsr_seed_string = sprintf($lfsr_fmt,$fiji_consts->{'LFSR_SEED'});
my $fault_detect_string = "00";
my $fiu_configs_string = join(" ,\n",@fiu_configs);
my $vhdl =<<"END_VHDL";
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.fault_selection_type_pkg.all;
package public_config_pkg is
------------------------------------------------------------------------------
-- Design configuration
------------------------------------------------------------------------------
-- The design's clock frequency
constant c_frequency : positive := $fiji_consts->{'FREQUENCY'};
-- The baud rate
constant c_baudrate : positive := $fiji_consts->{'BAUDRATE'};
-- The invert mask for the fault detection signals
constant c_fault_detect_invert_mask : std_logic_vector(1 downto 0) := $fault_detect_string;
------------------------------------------------------------------------------
-- LFSR configuration
------------------------------------------------------------------------------
-- Width of the LFSR for random FIU enable & stuck-open
constant c_lfsr_width : natural := $fiji_consts->{'LFSR_WIDTH'};
-- Polynomial for the LFSR
constant c_lfsr_poly : std_logic_vector(c_lfsr_width-1 downto 0) := $lfsr_poly_string;
-- Initial value for the LFSR
constant c_lfsr_seed : std_logic_vector(c_lfsr_width-1 downto 0) := $lfsr_seed_string;
------------------------------------------------------------------------------
-- Controller Configuration
------------------------------------------------------------------------------
-- Width of the timers in bytes.
constant c_timer_width : natural := $fiji_consts->{'TIMER_WIDTH'};
-- FIC -> DUT reset signal: active level
constant c_reset_dut_in_active : std_logic := '0';
-- reset duration
constant c_reset_dut_in_duration : positive := 4;
-- external reset signal: active level
constant c_reset_ext_active : std_logic := '0';
-- DUT -> FIC reset signal: active level
constant c_reset_dut_out_active : std_logic := '0';
-- active level of the external and internal triggers
constant c_trigger_ext_active : std_logic := '0';
constant c_trigger_dut_active : std_logic := '1';
-- hardware id
constant c_id : std_logic_vector(15 downto 0) := X"0123";
------------------------------------------------------------------------------
-- FIU Configuration
------------------------------------------------------------------------------
type t_single_fiu_record is record
fault_model : t_select_fault_models; --Select dynamic or single fault model. See fault_injection_unit
lfsr_mask : std_logic_vector(c_lfsr_width-1 downto 0); -- Select which LFSR bits to AND for Stuck-open fault
end record t_single_fiu_record;
type t_fiu_records is array (natural range <>) of t_single_fiu_record;
constant c_fiu_config : t_fiu_records := (
$fiu_configs_string
);
end package public_config_pkg;
END_VHDL
print $vhdl;
$logger->trace("=== Stopping execution ===");
return 0;
}
Log::Log4perl::init_and_watch('logger.conf', 'HUP');
exit main(@ARGV);
use FIJI::VHDL;
use Log::Log4perl qw(get_logger);
use Verilog::Netlist;
use Verilog::Getopt;
exit(main(@ARGV));
sub main ($) {
my $logger = get_logger();
Log::Log4perl::init_and_watch('logger.conf', 'HUP');
my $name = $0;
$name =~ s/\.p[lm]//;
my $cfgname = $name . ".cfg";
$logger->debug("=== Starting new execution of $name ===");
$logger->debug(sprintf("%d argument(s)%s", scalar(@_), scalar(@_) > 0 ? ": @_" : ""));
$logger->debug("Generating FIJI public config package");
FIJI::VHDL->generate_config_package("fiji.cfg", "fiji_public_config_pkg.vhd");
$logger->debug("Generating FIJI wrapper");
my %wrapper_config;
$wrapper_config{'dut_toplevel_module_name'} = "i2c_master_top";
$wrapper_config{'fiji_settings_filename'} = "fiji.cfg";
$wrapper_config{'vhdl_filename'} = "fiji_wrapper.vhd";
my $vqm_netlist = new Verilog::Netlist (options => $opt,
keep_comments=>1, # include comments in netlist
link_read_nonfatal=>1); # do not fail if module description not found
# read vqm file
$vqm_netlist->read_file (filename=>"test/synplify_i2c_mod.v") or die ("Could not read netlist.\n");
# Read in any sub-modules
$vqm_netlist->link();
#$vqm_netlist->lint(); # Optional, see docs; probably not wanted
$vqm_netlist->exit_if_error();
my $vqm_toplevel_module = $vqm_netlist->find_module($wrapper_config{'dut_toplevel_module_name'});
my $injected_idx = 0;
my $original_idx = 0;
foreach my $vqm_port ($vqm_toplevel_module->ports_ordered) {
if($vqm_port->name =~ m/.+inj_i$/) {
$vqm_port->userdata(FIJI::VHDL->FIJI_USERDATA_PORTTYPE,FIJI::VHDL->FIJI_PORTTYPE_MODIFIED);
$vqm_port->userdata(FIJI::VHDL->FIJI_USERDATA_FIU_INDEX,$injected_idx);
$injected_idx += 1;
} elsif($vqm_port->name =~ m/.+ori_o$/) {
$vqm_port->userdata(FIJI::VHDL->FIJI_USERDATA_PORTTYPE,FIJI::VHDL->FIJI_PORTTYPE_ORIGINAL);
$vqm_port->userdata(FIJI::VHDL->FIJI_USERDATA_FIU_INDEX,$original_idx);
$original_idx += 1;
}
}
my $clkport = $vqm_toplevel_module->find_port("dut_clk_o");
my $rstport = $vqm_toplevel_module->find_port("dut_rst_o");
print "bla ".FIJI::VHDL->FIJI_PORTTYPE_RESET_FROM_DUT."\n";
$clkport->userdata(FIJI::VHDL->FIJI_USERDATA_PORTTYPE,FIJI::VHDL->FIJI_PORTTYPE_CLOCK);
$rstport->userdata(FIJI::VHDL->FIJI_USERDATA_PORTTYPE,FIJI::VHDL->FIJI_PORTTYPE_RESET_FROM_DUT);
$vqm_netlist->link();
# END generate test netlist
$wrapper_config{'netlist'} = $vqm_netlist;
FIJI::VHDL->generate_wrapper_module(\%wrapper_config);
$logger->trace("=== Stopping execution ===");
}
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