Commit 4495bc4f authored by Stefan Tauner's avatar Stefan Tauner
Browse files

Shorten names of some constants

find * -type f \( -name "*.pm" -or -name "*.pl" -or -name "*.tst" -or -name "*.cfg" \) -print0 | parallel -q -0 sed -i -e 's/FAULT_DETECT_/FD_/g;s/RESET_/RST_/g;s/TRIGGER_/TRIG_/g;s/INSTRUMENTATION_/INST_/g;s/IMPLEMENTATION_/IMPL_/g;s/_DURATION/_DUR/g;s/_ACTIVE/_ACT/g;s/_CONFIG/_CFG/g;s/OPTIMIZATION_OFF/OPT_OFF/g;s/s_fiji_trigger_/s_fiji_trig_/g'
parent 3d219757
This diff is collapsed.
......@@ -77,7 +77,7 @@ set_global_assignment -name LL_ORIGIN X1_Y1 -section_id $FIJI_PART_NAME
set_instance_assignment -name LL_MEMBER_OF $FIJI_PART_NAME -to $FIJI_TO -section_id $FIJI_PART_NAME
END_LOCK
if ($cfg->{'mode'} eq "OPTIMIZATION_OFF") {
if ($cfg->{'mode'} eq "OPT_OFF") {
$txt .= $partitioning;
} elsif ($cfg->{'mode'} eq "FIX_PLACEMENT") {
$txt .= $partitioning . $area;
......@@ -116,7 +116,7 @@ define_attribute {v:work.$DUT_NAME} syn_netlist_hierarchy {1}
###==== END Attributes
END_OPTIMIZATION
if ($cfg->{'mode'} eq "OPTIMIZATION_OFF" || $cfg->{'mode'} eq "FIX_PLACEMENT") {
if ($cfg->{'mode'} eq "OPT_OFF" || $cfg->{'mode'} eq "FIX_PLACEMENT") {
$txt .= $no_optimization;
} elsif ($cfg->{'mode'} ne "ALLOW") {
$logger->error("Unknown SYNTHESIS_MODE " . $cfg->{'mode'});
......@@ -153,7 +153,7 @@ END_AREA
if ($cfg->{'mode'} eq "FIX_PLACEMENT") {
$txt .= $area;
} elsif ($cfg->{'mode'} ne "ALLOW" && $cfg->{'mode'} ne "OPTIMIZATION_OFF") {
} elsif ($cfg->{'mode'} ne "ALLOW" && $cfg->{'mode'} ne "OPT_OFF") {
$logger->error("Unknown SYNTHESIS_MODE " . $cfg->{'mode'});
return undef;
}
......
......@@ -410,11 +410,11 @@ sub _get_test_from_stdin {
}
printf("Enable reset (default: 0)? ");
$test->{'RESET_DUT_AFTER_CONFIG'} = <STDIN>;
last unless defined $test->{'RESET_DUT_AFTER_CONFIG'};
$test->{'RESET_DUT_AFTER_CONFIG'} =~ s/\R//g; # remove line breaks globally
$test->{'RESET_DUT_AFTER_CONFIG'} = ($test->{'RESET_DUT_AFTER_CONFIG'} =~ /1|yes|y/i) ? 1 : 0;
$logger->debug(sprintf("reset is %sabled.", $test->{'RESET_DUT_AFTER_CONFIG'} == 0 ? "dis" : "en"));
$test->{'RST_DUT_AFTER_CFG'} = <STDIN>;
last unless defined $test->{'RST_DUT_AFTER_CFG'};
$test->{'RST_DUT_AFTER_CFG'} =~ s/\R//g; # remove line breaks globally
$test->{'RST_DUT_AFTER_CFG'} = ($test->{'RST_DUT_AFTER_CFG'} =~ /1|yes|y/i) ? 1 : 0;
$logger->debug(sprintf("reset is %sabled.", $test->{'RST_DUT_AFTER_CFG'} == 0 ? "dis" : "en"));
return $test;
}
......@@ -492,7 +492,7 @@ sub update_prob($) {
# - test->{'TIMER_VALUE_1'}
# - test->{'TIMER_VALUE_2'}
# - test->{"FIU_[0..FIU_NUM]_FAULT_[0..CFGS_PER_MSG]"}
# - test->{'RESET_DUT_AFTER_CONFIG'}
# - test->{'RST_DUT_AFTER_CFG'}
# - test->{'TRIGGER'}
# @param port (optional) serial port to use
sub _download_test {
......@@ -526,7 +526,7 @@ sub _download_test {
my $trigger_en = ($test->{'TRIGGER'} ne "NONE") ? 1 : 0;
my $trigger_ext = ($test->{'TRIGGER'} eq "EXT") ? 1 : 0;
my $reset = $test->{'RESET_DUT_AFTER_CONFIG'};
my $reset = $test->{'RST_DUT_AFTER_CFG'};
$logger->debug(sprintf("trigger is %sabled.", $trigger_en == 0 ? "dis" : "en"));
if ($trigger_en == 1) {
......
......@@ -284,7 +284,7 @@ sub _add_port_to_hierarchy {
# decide direction
if ( $function == FIJI::VHDL->FIJI_PORTTYPE_MODIFIED
|| $function == FIJI::VHDL->FIJI_PORTTYPE_RESET_TO_DUT)
|| $function == FIJI::VHDL->FIJI_PORTTYPE_RST_TO_DUT)
{
$direction = "in";
} else {
......
......@@ -85,7 +85,7 @@ sub new ($;$$) {
$fiji_settings_ref->{'filename'} = File::Spec->curdir();
}
@base_resources = _est_resources(DESIGNMAP->{'FREQUENCY'}->{'default'}, DESIGNMAP->{'BAUDRATE'}->{'default'}, DESIGNMAP->{'TIMER_WIDTH'}->{'default'}, DESIGNMAP->{'RESET_DUT_IN_DURATION'}->{'default'}, DESIGNMAP->{'LFSR_WIDTH'}->{'default'}, 1, "logarithmic");
@base_resources = _est_resources(DESIGNMAP->{'FREQUENCY'}->{'default'}, DESIGNMAP->{'BAUDRATE'}->{'default'}, DESIGNMAP->{'TIMER_WIDTH'}->{'default'}, DESIGNMAP->{'RST_DUT_IN_DUR'}->{'default'}, DESIGNMAP->{'LFSR_WIDTH'}->{'default'}, 1, "logarithmic");
return ($fiji_settings_ref, $warn);
}
......@@ -678,7 +678,7 @@ sub _log2 {
return ($val > 0) ? (log($val) / log(2)) : 0;
}
## @function private _est_resources ($FREQUENCY, $BAUD, $TIMER_WIDTH, $RESET_CYCLES, $LFSR_WIDTH, $FIU_NUM, $algo)
## @function private _est_resources ($FREQUENCY, $BAUD, $TIMER_WIDTH, $RST_CYCLES, $LFSR_WIDTH, $FIU_NUM, $algo)
# @brief estimates the number of Registers and LUTs to implement FIJI logic with the given settings
#
# The function ant its parameters were determined by experiment & fitted by scipy.optimize.curve_fit
......@@ -686,7 +686,7 @@ sub _log2 {
# @param FREQUENCY the clock frequency the FIJI logic will run at in Hz
# @param BAUD the baud rate for DUT <-> FIJI communication
# @param TIMER_WIDTH the width of the injection timer (durations) in Bytes
# @param RESET_CYCLES the number of cycles to apply a FIJI-to-DUT reset
# @param RST_CYCLES the number of cycles to apply a FIJI-to-DUT reset
# @param LFSR_WIDTH width of the LFSR used for stuck-open emulation
# @param FIU_NUM the number of FIUs in the configuration
#
......@@ -694,7 +694,7 @@ sub _log2 {
sub _est_resources {
my $logger = get_logger("");
my ($FREQUENCY, $BAUD, $TIMER_WIDTH, $RESET_CYCLES, $LFSR_WIDTH, $FIU_NUM) = @_;
my ($FREQUENCY, $BAUD, $TIMER_WIDTH, $RST_CYCLES, $LFSR_WIDTH, $FIU_NUM) = @_;
# @FIXME where do we put these values? they are likely to change if the VHDL
# source is changed...
......@@ -715,13 +715,13 @@ sub _est_resources {
$logger->debug("TIMER_WIDTH $TIMER_WIDTH out of range for correct resource estimation (1 - 8)");
push @{$out_of_range}, "TIMER_WIDTH";
}
if ($RESET_CYCLES < 1 || $RESET_CYCLES > 16) {
$logger->debug("RESET_CYCLES $RESET_CYCLES out of range for correct resource estimation (1 - 16)");
push @{$out_of_range}, "RESET_CYCLES";
if ($RST_CYCLES < 1 || $RST_CYCLES > 16) {
$logger->debug("RST_CYCLES $RST_CYCLES out of range for correct resource estimation (1 - 16)");
push @{$out_of_range}, "RST_CYCLES";
}
if ($LFSR_WIDTH < 16 || $LFSR_WIDTH > 64) {
$logger->debug("LFSR_WIDTH $LFSR_WIDTH out of range for correct resource estimation (16 - 64)");
push @{$out_of_range}, "RESET_CYCLES";
push @{$out_of_range}, "RST_CYCLES";
}
if ($FIU_NUM < 1 || $FIU_NUM > 64) {
$logger->debug("FIU_NUM $FIU_NUM out of range for correct resource estimation (1 - 64)");
......@@ -732,7 +732,7 @@ sub _est_resources {
$registers += (3.16525787254e-08) * ($FREQUENCY) + (-8063276676.79) * (2**(-1.60957863771e-17 * $FREQUENCY));
$registers += (0.000329011902135) * ($BAUD) + (-705457194.107) * (2**(7.38032560255e-13 * $BAUD));
$registers += (86.8258719199) * ($TIMER_WIDTH) + (-424084.540754) * (2**(0.000218517717305 * $TIMER_WIDTH));
$registers += (5.02154556118) * ($RESET_CYCLES) + (51167.4447102) * (2**(-0.000135580209031 * $RESET_CYCLES));
$registers += (5.02154556118) * ($RST_CYCLES) + (51167.4447102) * (2**(-0.000135580209031 * $RST_CYCLES));
$registers += (-5.30893252274) * ($LFSR_WIDTH) + (-301970.077109) * (2**(-2.99010866996e-05 * $LFSR_WIDTH));
$registers += (13.746880792) * ($FIU_NUM) + (437.305954808) * (2**(-0.00583539664462 * $FIU_NUM));
......@@ -740,7 +740,7 @@ sub _est_resources {
$lut6 += (5.65349933334e-06) * ($FREQUENCY) + (-245548261.879) * (2**(3.26830064347e-14 * $FREQUENCY));
$lut6 += (-0.0602788840594) * ($BAUD) + (1868596655.23) * (2**(4.65257746085e-11 * $BAUD));
$lut6 += (9.04974779295) * ($TIMER_WIDTH) + (-123738.805411) * (2**(7.77721022021e-07 * $TIMER_WIDTH));
$lut6 += (0.156780025973) * ($RESET_CYCLES) + (-176988.018256) * (2**(1e-08 * $RESET_CYCLES));
$lut6 += (0.156780025973) * ($RST_CYCLES) + (-176988.018256) * (2**(1e-08 * $RST_CYCLES));
$lut6 += (-1.88257966999) * ($LFSR_WIDTH) + (-31351130.663) * (2**(-8.63995764468e-08 * $LFSR_WIDTH));
$lut6 += (3.95693187928) * ($FIU_NUM) + (2718.76465806) * (2**(-0.000895867386597 * $FIU_NUM));
......@@ -759,7 +759,7 @@ sub estimate_resources {
my $fiu_ref = $settings_ref->{'fius'};
my $fiu_num = @{$fiu_ref};
my @calcrv = _est_resources($consts_ref->{'FREQUENCY'}, $consts_ref->{'BAUDRATE'}, $consts_ref->{'TIMER_WIDTH'}, $consts_ref->{'RESET_DUT_IN_DURATION'}, $consts_ref->{'LFSR_WIDTH'}, $fiu_num, "logarithmic");
my @calcrv = _est_resources($consts_ref->{'FREQUENCY'}, $consts_ref->{'BAUDRATE'}, $consts_ref->{'TIMER_WIDTH'}, $consts_ref->{'RST_DUT_IN_DUR'}, $consts_ref->{'LFSR_WIDTH'}, $fiu_num, "logarithmic");
my $rv = {
regs => sprintf("%.2f", $calcrv[0] / $base_resources[0]),
......
......@@ -796,7 +796,7 @@ sub export_as_sim_script {
}
# @FIXME translate in actual Questasim tcl syntax
if ($global_settings_ref->{'design'}->{'RESET_DUT_OUT_EN'} == 1) {
if ($global_settings_ref->{'design'}->{'RST_DUT_OUT_EN'} == 1) {
$script_text .= <<"END_RST";
set testbench_name \$1;
set start 0;
......@@ -824,7 +824,7 @@ proc randbit mask {
return expr {(\$lfsrval & \$mask) > 0};
}
when -label rst {\"\$testbench_name|$global_settings_ref->{'design'}->{'RESET_DUT_OUT_NAME'}\" == not $global_settings_ref->{'design'}->{'RESET_DUT_IN_ACTIVE'} &&
when -label rst {\"\$testbench_name|$global_settings_ref->{'design'}->{'RST_DUT_OUT_NAME'}\" == not $global_settings_ref->{'design'}->{'RST_DUT_IN_ACT'} &&
\"\$testbench_name|$global_settings_ref->{'design'}->{'CLOCK_NET'}\" == 1 && \"\$start == 0\"} {
set start 1;
nowhen rst;
......@@ -866,21 +866,21 @@ END_RST
my $test = @{$self->{'tests'}}[$ti];
if ($test->{'RESET_DUT_AFTER_CONFIG'} == 1) {
$script_text .= $indent . "force -freeze " . $global_settings_ref->{'design'}->{'RESET_DUT_IN_NAME'};
$script_text .= " '" . $global_settings_ref->{'design'}->{'RESET_DUT_IN_ACTIVE'} . "'";
$script_text .= " -cancel " . ($global_settings_ref->{'design'}->{'RESET_DUT_IN_DURATION'} * (10**12) / ($global_settings_ref->{'design'}->{'FREQUENCY'})) . " ps; \n";
$script_text .= $indent . "when -label dutrst_$absolute_test_index \"\$now == " . ($global_settings_ref->{'design'}->{'RESET_DUT_IN_DURATION'} * (10**12) / ($global_settings_ref->{'design'}->{'FREQUENCY'})) . " ps\" {\n";
if ($test->{'RST_DUT_AFTER_CFG'} == 1) {
$script_text .= $indent . "force -freeze " . $global_settings_ref->{'design'}->{'RST_DUT_IN_NAME'};
$script_text .= " '" . $global_settings_ref->{'design'}->{'RST_DUT_IN_ACT'} . "'";
$script_text .= " -cancel " . ($global_settings_ref->{'design'}->{'RST_DUT_IN_DUR'} * (10**12) / ($global_settings_ref->{'design'}->{'FREQUENCY'})) . " ps; \n";
$script_text .= $indent . "when -label dutrst_$absolute_test_index \"\$now == " . ($global_settings_ref->{'design'}->{'RST_DUT_IN_DUR'} * (10**12) / ($global_settings_ref->{'design'}->{'FREQUENCY'})) . " ps\" {\n";
}
my ($tr, $act);
if ($test->{'TRIGGER'} ne "NONE") {
if ($test->{'TRIGGER'} eq "INT") {
$tr = $global_settings_ref->{'design'}->{'TRIGGER_DUT_NAME'};
$act = $global_settings_ref->{'design'}->{'TRIGGER_DUT_ACTIVE'};
$tr = $global_settings_ref->{'design'}->{'TRIG_DUT_NAME'};
$act = $global_settings_ref->{'design'}->{'TRIG_DUT_ACT'};
} else {
$tr = $global_settings_ref->{'design'}->{'TRIGGER_DUT_NAME'};
$act = $global_settings_ref->{'design'}->{'TRIGGER_EXT_ACTIVE'};
$tr = $global_settings_ref->{'design'}->{'TRIG_DUT_NAME'};
$act = $global_settings_ref->{'design'}->{'TRIG_EXT_ACT'};
}
$script_text .= ($indent x 2) . "when -label trigger_$absolute_test_index {$tr = $act} {\n";
}
......@@ -923,7 +923,7 @@ END_RST
$script_text .= ($indent) . "when -label action_" . ($absolute_test_index) . "_$ci \"\$now == $time ps\" { \n" . $action_text . ($indent) . "};\n" if $action_text ne "";
}
$script_text .= "$indent};\n" if ($test->{'TRIGGER'} ne "NONE");
$script_text .= "$indent};\n" if $test->{'RESET_DUT_AFTER_CONFIG'} == 1;
$script_text .= "$indent};\n" if $test->{'RST_DUT_AFTER_CFG'} == 1;
$script_text .= "};\n";
$absolute_test_index++;
}
......@@ -938,17 +938,17 @@ END_RST
# @brief randomly generate a test pattern
#
# Depending on:
# - MIN_DURATION_T1
# - MIN_DURATION_T2
# - MAX_DURATION_T1
# - MAX_DURATION_T2
# - MIN_DUR_T1
# - MIN_DUR_T2
# - MAX_DUR_T1
# - MAX_DUR_T2
# - PROB_xxx
#
# @param global_settings_ref FIJI hardware settings
#
# @returns STRING if an error occurred
# @returns a Hash describing the test if successful. The hash contains the keys
# - 'RESET_DUT_AFTER_CONFIG' if the DUT shall be reset after configuration (always 0)
# - 'RST_DUT_AFTER_CFG' if the DUT shall be reset after configuration (always 0)
# - 'TRIGGER' if FIJI shall wait for an external or internal trigger (always "NONE")
# - 'TIMER_VALUE_(1...n)' values for the different durations
# - 'FIU_(1...m)_FAULT_(1...n)' fault configuration for the respective FIU in the respective phase
......@@ -960,28 +960,28 @@ sub make_random_test {
# @TODO: Move parameter validation somewhere else?
for (my $pi = 1 ; $pi <= $global_settings_ref->{'design'}->{'CFGS_PER_MSG'} ; $pi++) {
if ($self->{'design'}->{'MAX_DURATION_T' . $pi} < $self->{'design'}->{'MIN_DURATION_T' . $pi}) {
if ($self->{'design'}->{'MAX_DUR_T' . $pi} < $self->{'design'}->{'MIN_DUR_T' . $pi}) {
$msg = "Maximum duration " . ($pi + 1) . " must be greater than or equal to minimum duration " . ($pi + 1);
return $msg;
} elsif ($self->{'design'}->{'MAX_DURATION_T' . $pi} < 0 || $self->{'design'}->{'MIN_DURATION_T' . $pi} < 0) {
} elsif ($self->{'design'}->{'MAX_DUR_T' . $pi} < 0 || $self->{'design'}->{'MIN_DUR_T' . $pi} < 0) {
$msg = "Durations must be positive.";
return $msg;
} elsif ($self->{'design'}->{'MAX_DURATION_T' . $pi} > 2**($global_settings_ref->{'design'}->{'TIMER_WIDTH'} * 8) - 1) {
} elsif ($self->{'design'}->{'MAX_DUR_T' . $pi} > 2**($global_settings_ref->{'design'}->{'TIMER_WIDTH'} * 8) - 1) {
$msg = "Durations must be at most " . $global_settings_ref->{'design'}->{'TIMER_WIDTH'} . " bytes.";
return $msg;
}
}
if (defined $is_initial && $is_initial) {
$test->{'RESET_DUT_AFTER_CONFIG'} = $self->{'design'}->{'INITIAL_RESET'};
$test->{'RST_DUT_AFTER_CFG'} = $self->{'design'}->{'INITIAL_RESET'};
$test->{'TRIGGER'} = $self->{'design'}->{'INITIAL_TRIGGER'};
} else {
$test->{'RESET_DUT_AFTER_CONFIG'} = 0;
$test->{'RST_DUT_AFTER_CFG'} = 0;
$test->{'TRIGGER'} = "NONE";
}
for (my $pi = 1 ; $pi <= $global_settings_ref->{'design'}->{'CFGS_PER_MSG'} ; $pi++) {
$test->{"TIMER_VALUE_${pi}"} = int(rand($self->{'design'}->{'MAX_DURATION_T' . $pi} - $self->{'design'}->{'MIN_DURATION_T' . $pi}) + $self->{'design'}->{'MIN_DURATION_T' . $pi});
$test->{"TIMER_VALUE_${pi}"} = int(rand($self->{'design'}->{'MAX_DUR_T' . $pi} - $self->{'design'}->{'MIN_DUR_T' . $pi}) + $self->{'design'}->{'MIN_DUR_T' . $pi});
}
if ($self->{'design'}->{'MULTIFAULT'} == 1) {
......
......@@ -45,14 +45,14 @@ sub export_timing {
$vlog .= $indent."wait until ";
my $n = $trigger;
$n =~ s/EXT/EXT_IN/;
my $edge = ($settings_ref->{'design'}->{"TRIGGER_${trigger}_ACTIVE"} == 0) ? "neg" : "pos";
$vlog .= '@('.$edge.'edge '.$settings_ref->{'design'}->{'TRIGGER_'.$n.'_NAME'}.');\n';
my $edge = ($settings_ref->{'design'}->{"TRIG_${trigger}_ACT"} == 0) ? "neg" : "pos";
$vlog .= '@('.$edge.'edge '.$settings_ref->{'design'}->{'TRIG_'.$n.'_NAME'}.');\n';
$vlog .= $indent."#".(2*$period)."$si; // trigger synchronization/edge detection\n";
}
if (defined $reset && $reset != 0) {
$vlog .= $indent."// BEGIN reset time ($settings_ref->{'design'}->{'RESET_DUT_IN_DURATION'})\n";
$vlog .= $indent."#".(($settings_ref->{'design'}->{'RESET_DUT_IN_DURATION'})*$period)."$si;\n";
$vlog .= $indent."// BEGIN reset time ($settings_ref->{'design'}->{'RST_DUT_IN_DUR'})\n";
$vlog .= $indent."#".(($settings_ref->{'design'}->{'RST_DUT_IN_DUR'})*$period)."$si;\n";
}
$vlog .= $indent."// BEGIN timer time ($timer)\n";
......@@ -190,8 +190,8 @@ $vlog .=<<"END_HDR";
END_HDR
my @conditions;
push @conditions, "(.add.some.hierarchy.here.$global_settings_ref->{'design'}->{'RESET_EXT_IN_NAME'} = 1'b$global_settings_ref->{'design'}->{'RESET_EXT_ACTIVE'})" if $global_settings_ref->{'design'}->{'RESET_EXT_EN'};
push @conditions, "(.add.some.hierarchy.here.$global_settings_ref->{'design'}->{'RESET_DUT_OUT_NAME'} = 1'b$global_settings_ref->{'design'}->{'RESET_DUT_OUT_ACTIVE'})" if $global_settings_ref->{'design'}->{'RESET_DUT_OUT_EN'};
push @conditions, "(.add.some.hierarchy.here.$global_settings_ref->{'design'}->{'RST_EXT_IN_NAME'} = 1'b$global_settings_ref->{'design'}->{'RST_EXT_ACT'})" if $global_settings_ref->{'design'}->{'RST_EXT_EN'};
push @conditions, "(.add.some.hierarchy.here.$global_settings_ref->{'design'}->{'RST_DUT_OUT_NAME'} = 1'b$global_settings_ref->{'design'}->{'RST_DUT_OUT_ACT'})" if $global_settings_ref->{'design'}->{'RST_DUT_OUT_EN'};
$vlog .= " assign s_reset = (".join(" or ",@conditions).");";
$vlog .=<<"END_HDR";
......@@ -205,7 +205,7 @@ END_HDR
$vlog .= " add.some.hierarchy.here.FIU_${fi}_select <= 3'd0; // NONE\n";
}
if ($global_settings_ref->{'design'}->{'RESET_EXT_EN'} || $global_settings_ref->{'design'}->{'RESET_DUT_OUT_EN'}) {
if ($global_settings_ref->{'design'}->{'RST_EXT_EN'} || $global_settings_ref->{'design'}->{'RST_DUT_OUT_EN'}) {
$vlog .= " @(negedge s_reset);\n";
$vlog .= " @(posedge s_clk); // synchronize with clock\n";
}
......@@ -220,7 +220,7 @@ END_HDR
push @fault_vlog, " // BEGIN Test $ti";
push @fault_vlog, " \$display(\"[FIJI] BEGIN Test $ti\");";
my $test = @{$tests->{'tests'}}[$ti];
my $rst = ($test->{"RESET_DUT_AFTER_CONFIG"}) ? "true" : "false";
my $rst = ($test->{"RST_DUT_AFTER_CFG"}) ? "true" : "false";
my $trig = ($test->{"TRIGGER"});
# calculate how long it takes after finishing the previous
......
......@@ -52,16 +52,16 @@ END_CLKCNTR
$vhdl .= $indent."wait until ";
my $n = $trigger;
$n =~ s/EXT/EXT_IN/;
$vhdl .= $settings_ref->{'design'}->{'TRIGGER_'.$n.'_NAME'}.' = ';
$vhdl .= "'".$settings_ref->{'design'}->{"TRIGGER_${trigger}_ACTIVE"}."';\n";
$vhdl .= $settings_ref->{'design'}->{'TRIG_'.$n.'_NAME'}.' = ';
$vhdl .= "'".$settings_ref->{'design'}->{"TRIG_${trigger}_ACT"}."';\n";
# $vhdl .= $indent."wait for 2 * ($period $si); -- trigger synchronization/edge detection\n";
$vhdl .= sprintf("--trigger synchronization/edge detection\n".$clkcntr, 2);
}
if (defined $reset && $reset != 0) {
$vhdl .= $indent."-- BEGIN reset time ($settings_ref->{'design'}->{'RESET_DUT_IN_DURATION'})\n";
# $vhdl .= $indent."wait for ".(($settings_ref->{'design'}->{'RESET_DUT_IN_DURATION'})*$period)." $si;\n";
$vhdl .= sprintf($clkcntr, $settings_ref->{'design'}->{'RESET_DUT_IN_DURATION'})
$vhdl .= $indent."-- BEGIN reset time ($settings_ref->{'design'}->{'RST_DUT_IN_DUR'})\n";
# $vhdl .= $indent."wait for ".(($settings_ref->{'design'}->{'RST_DUT_IN_DUR'})*$period)." $si;\n";
$vhdl .= sprintf($clkcntr, $settings_ref->{'design'}->{'RST_DUT_IN_DUR'})
}
$vhdl .= $indent."-- BEGIN timer time ($timer)\n";
......@@ -203,8 +203,8 @@ $vhdl .=<<"END_HDR";
END_HDR
my @conditions;
push @conditions, "(<< signal .add.some.hierarchy.here.$global_settings_ref->{'design'}->{'RESET_EXT_IN_NAME'} : std_logic >> = '$global_settings_ref->{'design'}->{'RESET_EXT_ACTIVE'}')" if $global_settings_ref->{'design'}->{'RESET_EXT_EN'};
push @conditions, "(<< signal .add.some.hierarchy.here.$global_settings_ref->{'design'}->{'RESET_DUT_OUT_NAME'} : std_logic >> = '$global_settings_ref->{'design'}->{'RESET_DUT_OUT_ACTIVE'}')" if $global_settings_ref->{'design'}->{'RESET_DUT_OUT_EN'};
push @conditions, "(<< signal .add.some.hierarchy.here.$global_settings_ref->{'design'}->{'RST_EXT_IN_NAME'} : std_logic >> = '$global_settings_ref->{'design'}->{'RST_EXT_ACT'}')" if $global_settings_ref->{'design'}->{'RST_EXT_EN'};
push @conditions, "(<< signal .add.some.hierarchy.here.$global_settings_ref->{'design'}->{'RST_DUT_OUT_NAME'} : std_logic >> = '$global_settings_ref->{'design'}->{'RST_DUT_OUT_ACT'}')" if $global_settings_ref->{'design'}->{'RST_DUT_OUT_EN'};
$vhdl .= " s_reset <= true when (".join(" or ",@conditions).") else false;\n";
$vhdl .=<<"END_HDR";
......@@ -216,7 +216,7 @@ $vhdl .=<<"END_HDR";
END_HDR
if ($global_settings_ref->{'design'}->{'RESET_EXT_EN'} || $global_settings_ref->{'design'}->{'RESET_DUT_OUT_EN'}) {
if ($global_settings_ref->{'design'}->{'RST_EXT_EN'} || $global_settings_ref->{'design'}->{'RST_DUT_OUT_EN'}) {
$vhdl .= " wait until s_reset = false;\n";
$vhdl .= " wait until s_clk = '1'; -- synchronize with clock\n";
}
......@@ -231,7 +231,7 @@ END_HDR
push @fault_vhdl, " -- BEGIN Test $ti";
push @fault_vhdl, " report \"[FIJI] BEGIN Test $ti\" severity note;";
my $test = @{$tests->{'tests'}}[$ti];
my $rst = ($test->{"RESET_DUT_AFTER_CONFIG"}) ? "true" : "false";
my $rst = ($test->{"RST_DUT_AFTER_CFG"}) ? "true" : "false";
my $trig = ($test->{"TRIGGER"});
# calculate how long it takes after finishing the previous
......@@ -379,8 +379,8 @@ begin
END_HDR
my @conditions;
push @conditions, "(s_fiji_reset_ext_i = '$design_ref->{'RESET_EXT_ACTIVE'}')" if $global_settings_ref->{'design'}->{'RESET_EXT_EN'};
push @conditions, "(s_fiji_reset_dut_out_i = '$design_ref->{'RESET_DUT_OUT_ACTIVE'}')" if $global_settings_ref->{'design'}->{'RESET_DUT_OUT_EN'};
push @conditions, "(s_fiji_reset_ext_i = '$design_ref->{'RST_EXT_ACT'}')" if $global_settings_ref->{'design'}->{'RST_EXT_EN'};
push @conditions, "(s_fiji_reset_dut_out_i = '$design_ref->{'RST_DUT_OUT_ACT'}')" if $global_settings_ref->{'design'}->{'RST_DUT_OUT_EN'};
$vhdl .= " s_reset <= true when (".join(" or ",@conditions).") else false;\n";
$vhdl .=<<"END_HDR";
......@@ -423,7 +423,7 @@ $vhdl .=<<"END_HDR";
END_HDR
if ($global_settings_ref->{'design'}->{'RESET_EXT_EN'} || $global_settings_ref->{'design'}->{'RESET_DUT_OUT_EN'}) {
if ($global_settings_ref->{'design'}->{'RST_EXT_EN'} || $global_settings_ref->{'design'}->{'RST_DUT_OUT_EN'}) {
$vhdl .= " wait until s_reset = false;\n";
$vhdl .= " wait until s_fiji_clk_i = '1'; -- synchronize with clock\n";
}
......@@ -443,7 +443,7 @@ END_HDR
push @fault_vhdl, " -- BEGIN Test $ti";
push @fault_vhdl, " report \"[FIJI] BEGIN Test $ti\" severity note;";
my $test = @{$tests->{'tests'}}[$ti];
my $rst = ($test->{"RESET_DUT_AFTER_CONFIG"}) ? "true" : "false";
my $rst = ($test->{"RST_DUT_AFTER_CFG"}) ? "true" : "false";
my $trig = ($test->{"TRIGGER"});
# calculate how long it takes after finishing the previous
......@@ -533,7 +533,7 @@ sub export_as_vhd_pkg {
#my $tests = "";
my $faults = "";
my $test = @{$self->{'tests'}}[$ti];
my $rst = ($test->{"RESET_DUT_AFTER_CONFIG"}) ? "true" : "false";
my $rst = ($test->{"RST_DUT_AFTER_CFG"}) ? "true" : "false";
for (my $ci = 1 ; $ci <= $global_settings_ref->{'design'}->{'CFGS_PER_MSG'} ; $ci++) {
$faults .= " $ci => (\n";
for (my $fi = 0 ; $fi < $global_settings_ref->{'design'}->{'FIU_NUM'} ; $fi++) {
......
......@@ -43,10 +43,10 @@ use enum qw(FIJI_USERDATA_PORTTYPE FIJI_USERDATA_PREV_PORTNAME FIJI_USERDATA_FIU
# FIJI_PORTTYPE_MODIFIED: modified net input to DUT
# FIJI_PORTTYPE_ORIGINAL: original net output to FIJI
# FIJI_PORTTYPE_FAULT_DETECTION: fault detection net output to FIJI
# FIJI_PORTTYPE_TRIGGER_FROM_DUT: internal trigger from DUT to FIJI
# FIJI_PORTTYPE_RESET_FROM_DUT: internal reset from DUT to FIJI
# FIJI_PORTTYPE_RESET_TO_DUT: internal reset from FIJI to DUT
use enum qw(FIJI_PORTTYPE_CLOCK FIJI_PORTTYPE_MODIFIED FIJI_PORTTYPE_ORIGINAL FIJI_PORTTYPE_FAULT_DETECTION FIJI_PORTTYPE_TRIGGER_FROM_DUT FIJI_PORTTYPE_RESET_FROM_DUT FIJI_PORTTYPE_RESET_TO_DUT);
# FIJI_PORTTYPE_TRIG_FROM_DUT: internal trigger from DUT to FIJI
# FIJI_PORTTYPE_RST_FROM_DUT: internal reset from DUT to FIJI
# FIJI_PORTTYPE_RST_TO_DUT: internal reset from FIJI to DUT
use enum qw(FIJI_PORTTYPE_CLOCK FIJI_PORTTYPE_MODIFIED FIJI_PORTTYPE_ORIGINAL FIJI_PORTTYPE_FAULT_DETECTION FIJI_PORTTYPE_TRIG_FROM_DUT FIJI_PORTTYPE_RST_FROM_DUT FIJI_PORTTYPE_RST_TO_DUT);
# Default values hash for signal and instantiation names, and the trigger and reset values
use constant FIJI_DEFAULTS => {
......@@ -56,19 +56,19 @@ use constant FIJI_DEFAULTS => {
FIJI_INST_NAME => "i_FIJI",
FIJI_WRAPPER_NAME => "fiji_top",
FIJI_WRAPPER_CLOCK_SIGNAL_NAME => "s_fiji_clk",
FIJI_WRAPPER_ORIGINAL_SIGNAL_NAME => "s_fiji_original",
FIJI_WRAPPER_MODIFIED_SIGNAL_NAME => "s_fiji_modified",
FIJI_WRAPPER_FAULT_SIGNAL_NAME => "s_fiji_fault_detect",
FIJI_WRAPPER_TRIGGER_DUT_SIGNAL_NAME => "s_fiji_trigger_from_dut",
FIJI_WRAPPER_TRIGGER_EXT_SIGNAL_NAME => "s_fiji_trigger_ext",
FIJI_WRAPPER_RESET_FROM_DUT_SIGNAL_NAME => "s_fiji_reset_from_dut",
FIJI_WRAPPER_RESET_TO_DUT_SIGNAL_NAME => "s_fiji_reset_to_dut",
FIJI_WRAPPER_RESET_EXT_SIGNAL_NAME => "s_fiji_reset_ext",
RESET_EXT_IN_NAME => "s_fiji_reset",
FIJI_WRAPPER_CLOCK_SIGNAL_NAME => "s_fiji_clk",
FIJI_WRAPPER_ORIGINAL_SIGNAL_NAME => "s_fiji_original",
FIJI_WRAPPER_MODIFIED_SIGNAL_NAME => "s_fiji_modified",
FIJI_WRAPPER_FAULT_SIGNAL_NAME => "s_fiji_fault_detect",
FIJI_WRAPPER_TRIG_DUT_SIGNAL_NAME => "s_fiji_trig_from_dut",
FIJI_WRAPPER_TRIG_EXT_SIGNAL_NAME => "s_fiji_trig_ext",
FIJI_WRAPPER_RST_FROM_DUT_SIGNAL_NAME => "s_fiji_reset_from_dut",
FIJI_WRAPPER_RST_TO_DUT_SIGNAL_NAME => "s_fiji_reset_to_dut",
FIJI_WRAPPER_RST_EXT_SIGNAL_NAME => "s_fiji_reset_ext",
RST_EXT_IN_NAME => "s_fiji_reset",
FIJI_TRIGGER_EXT_ASSIGNMENT => "not(c_trigger_ext_active)",
FIJI_RESET_EXT_ASSIGNMENT => "not(c_reset_ext_active)",
FIJI_TRIG_EXT_ASSIGNMENT => "not(c_trigger_ext_active)",
FIJI_RST_EXT_ASSIGNMENT => "not(c_reset_ext_active)",
FIJI_FAULT_INJECTION_GEN_LABEL => "gen_fault_injection",
FIJI_NO_FAULT_INJECTION_GEN_LABEL => "gen_no_fault_injection",
......@@ -122,15 +122,15 @@ END_FIU
# invert is given as 2-bit binary mask
# need to do this because fault detection invert can be specified even if channel is not enabled
my $invert1 = ($fiji_consts->{'FAULT_DETECT_1_EN'}) ? $fiji_consts->{'FAULT_DETECT_1_INVERT'} : 0;
my $invert2 = ($fiji_consts->{'FAULT_DETECT_2_EN'}) ? $fiji_consts->{'FAULT_DETECT_2_INVERT'} : 0;
my $invert1 = ($fiji_consts->{'FD_1_EN'}) ? $fiji_consts->{'FD_1_INVERT'} : 0;
my $invert2 = ($fiji_consts->{'FD_2_EN'}) ? $fiji_consts->{'FD_2_INVERT'} : 0;
my $fault_detect_string = sprintf("%01d%01d", $invert2, $invert1);
my $fiu_configs_string = join(" ,\n", @fiu_configs);
my $vhdl_id = sprintf("X\"%04x\"", $fiji_consts->{'ID'});
my $gentime = localtime;
my $reset_dut_in_duration = ($fiji_consts->{'RESET_DUT_IN_EN'} eq 1) ? $fiji_consts->{'RESET_DUT_IN_DURATION'} : 1;
my $reset_dut_in_duration = ($fiji_consts->{'RST_DUT_IN_EN'} eq 1) ? $fiji_consts->{'RST_DUT_IN_DUR'} : 1;
$logger->debug(sprintf("Generating VHDL text.\n"));
......@@ -191,20 +191,20 @@ package public_config_pkg is
constant c_timer_width : natural := $fiji_consts->{'TIMER_WIDTH'};
-- FIC -> DUT reset signal: active level
constant c_reset_dut_in_active : std_logic := '$fiji_consts->{'RESET_DUT_IN_ACTIVE'}';
constant c_reset_dut_in_active : std_logic := '$fiji_consts->{'RST_DUT_IN_ACT'}';
-- reset duration
constant c_reset_dut_in_duration : positive := $reset_dut_in_duration;
-- external reset signal: active level
constant c_reset_ext_active : std_logic := '$fiji_consts->{'RESET_EXT_ACTIVE'}';
constant c_reset_ext_active : std_logic := '$fiji_consts->{'RST_EXT_ACT'}';
-- DUT -> FIC reset signal: active level
constant c_reset_dut_out_active : std_logic := '$fiji_consts->{'RESET_DUT_OUT_ACTIVE'}';
constant c_reset_dut_out_active : std_logic := '$fiji_consts->{'RST_DUT_OUT_ACT'}';
-- active level of the external and internal triggers
constant c_trigger_ext_active : std_logic := '$fiji_consts->{'TRIGGER_EXT_ACTIVE'}';
constant c_trigger_dut_active : std_logic := '$fiji_consts->{'TRIGGER_DUT_ACTIVE'}';
constant c_trigger_ext_active : std_logic := '$fiji_consts->{'TRIG_EXT_ACT'}';
constant c_trigger_dut_active : std_logic := '$fiji_consts->{'TRIG_DUT_ACT'}';
-- hardware id
constant c_id : std_logic_vector(15 downto 0) := $vhdl_id;
......@@ -298,11 +298,11 @@ sub generate_wrapper_module {
my $fiji_original_signal_name = FIJI_DEFAULTS->{'FIJI_WRAPPER_ORIGINAL_SIGNAL_NAME'};
my $fiji_modified_signal_name = FIJI_DEFAULTS->{'FIJI_WRAPPER_MODIFIED_SIGNAL_NAME'};
my $fiji_fault_detection_signal_name = FIJI_DEFAULTS->{'FIJI_WRAPPER_FAULT_SIGNAL_NAME'};
my $fiji_trigger_from_dut_signal_name = FIJI_DEFAULTS->{'FIJI_WRAPPER_TRIGGER_DUT_SIGNAL_NAME'};
my $fiji_trigger_ext_signal_name = FIJI_DEFAULTS->{'FIJI_WRAPPER_TRIGGER_EXT_SIGNAL_NAME'};
my $fiji_reset_from_dut_signal_name = FIJI_DEFAULTS->{'FIJI_WRAPPER_RESET_FROM_DUT_SIGNAL_NAME'};
my $fiji_reset_to_dut_signal_name = FIJI_DEFAULTS->{'FIJI_WRAPPER_RESET_TO_DUT_SIGNAL_NAME'};
my $fiji_reset_ext_signal_name = FIJI_DEFAULTS->{'FIJI_WRAPPER_RESET_EXT_SIGNAL_NAME'};
my $fiji_trigger_from_dut_signal_name = FIJI_DEFAULTS->{'FIJI_WRAPPER_TRIG_DUT_SIGNAL_NAME'};
my $fiji_trigger_ext_signal_name = FIJI_DEFAULTS->{'FIJI_WRAPPER_TRIG_EXT_SIGNAL_NAME'};
my $fiji_reset_from_dut_signal_name = FIJI_DEFAULTS->{'FIJI_WRAPPER_RST_FROM_DUT_SIGNAL_NAME'};
my $fiji_reset_to_dut_signal_name = FIJI_DEFAULTS->{'FIJI_WRAPPER_RST_TO_DUT_SIGNAL_NAME'};
my $fiji_reset_ext_signal_name = FIJI_DEFAULTS->{'FIJI_WRAPPER_RST_EXT_SIGNAL_NAME'};
my $gen_fault_injection_label = FIJI_DEFAULTS->{'FIJI_FAULT_INJECTION_GEN_LABEL'};
my $gen_no_fault_injection_label = FIJI_DEFAULTS->{'FIJI_NO_FAULT_INJECTION_GEN_LABEL'};
my $attributes = FIJI_DEFAULTS->{'FIJI_WRAPPER_ATTRIBUTES'};
......@@ -327,13 +327,13 @@ sub generate_wrapper_module {
push @ext_ports, _vhdl_escape_identifier($tx_name) . ": out std_logic";
push @ext_ports, _vhdl_escape_identifier($rx_name) . ": in std_logic";
if ($fiji_consts->{'RESET_EXT_EN'}) {
my $re = _vhdl_escape_identifier((defined $fiji_consts->{'RESET_EXT_IN_NAME'}) ? $fiji_consts->{'RESET_EXT_IN_NAME'} : FIJI_DEFAULTS->{'RESET_EXT_IN_NAME'});
if ($fiji_consts->{'RST_EXT_EN'}) {
my $re = _vhdl_escape_identifier((defined $fiji_consts->{'RST_EXT_IN_NAME'}) ? $fiji_consts->{'RST_EXT_IN_NAME'} : FIJI_DEFAULTS->{'RST_EXT_IN_NAME'});
push @ext_ports, "$re : in std_logic";
$reset_ext_assignment = $re;
}
if ($fiji_consts->{'TRIGGER_EXT_EN'}) {
my $te = _vhdl_escape_identifier((defined $fiji_consts->{'TRIGGER_EXT_IN_NAME'}) ? $fiji_consts->{'TRIGGER_EXT_IN_NAME'} : FIJI_DEFAULTS->{'TRIGGER_EXT_IN_NAME'});
if ($fiji_consts->{'TRIG_EXT_EN'}) {
my $te = _vhdl_escape_identifier((defined $fiji_consts->{'TRIG_EXT_IN_NAME'}) ? $fiji_consts->{'TRIG_EXT_IN_NAME'} : FIJI_DEFAULTS->{'TRIG_EXT_IN_NAME'});
push @ext_ports, "$te : in std_logic";
$trigger_ext_assignment = $te;
}
......@@ -370,11 +370,11 @@ sub generate_wrapper_module {
} elsif ($fiji_porttype == FIJI_PORTTYPE_FAULT_DETECTION) {
return "Port " . ($port->name) . " has no fd_idx assignment" unless (defined $fd_idx);
push @dut_port_maps, (_vhdl_escape_identifier($port->name) . " => $fiji_fault_detection_signal_name(" . $fd_idx . ")");
} elsif ($fiji_porttype == FIJI_PORTTYPE_TRIGGER_FROM_DUT) {
} elsif ($fiji_porttype == FIJI_PORTTYPE_TRIG_FROM_DUT) {
push @dut_port_maps, (_vhdl_escape_identifier($port->name) . " => $fiji_trigger_from_dut_signal_name");
} elsif ($fiji_porttype == FIJI_PORTTYPE_RESET_FROM_DUT) {
} elsif ($fiji_porttype == FIJI_PORTTYPE_RST_FROM_DUT) {
push @dut_port_maps, (_vhdl_escape_identifier($port->name) . " => $fiji_reset_from_dut_signal_name");
} elsif ($fiji_porttype == FIJI_PORTTYPE_RESET_TO_DUT) {
} elsif ($fiji_porttype == FIJI_PORTTYPE_RST_TO_DUT) {
push @dut_port_maps, (_vhdl_escape_identifier($port->name) . " => $fiji_reset_to_dut_signal_name");
} else {
$logger->error("Unknown fiji_porttype assignment: $fiji_porttype");
......@@ -445,11 +445,11 @@ architecture wrap of $wrapper_name is
signal $fiji_trigger_ext_signal_name : std_logic;
signal $fiji_reset_ext_signal_name : std_logic;
signal $fiji_clock_signal_name : std_logic;
signal $fiji_clock_signal_name : std_logic;
signal $fiji_reset_from_dut_signal_name : std_logic := not(c_reset_dut_out_active);
signal $fiji_reset_to_dut_signal_name : std_logic;
signal $fiji_trigger_from_dut_signal_name : std_logic := not(c_trigger_dut_active);
signal $fiji_fault_detection_signal_name : std_logic_vector(c_num_fault_detect_nets-1 downto 0) := (others => '0');
signal $fiji_fault_detection_signal_name : std_logic_vector(c_num_fault_detect_nets-1 downto 0) := (others => '0');
signal $fiji_original_signal_name : std_logic_vector(c_fiu_config'length-1 downto 0);
signal $fiji_modified_signal_name : std_logic_vector(c_fiu_config'length-1 downto 0);
......@@ -473,8 +473,8 @@ begin
s_fiji_reset_dut_in_o => $fiji_reset_to_dut_signal_name,
s_fiji_rx_i => $rx_name,
s_fiji_tx_o => $tx_name,
s_fiji_trigger_ext_i => $fiji_trigger_ext_signal_name,
s_fiji_trigger_dut_i => $fiji_trigger_from_dut_signal_name,
s_fiji_trig_ext_i => $fiji_trigger_ext_signal_name,
s_fiji_trig_dut_i => $fiji_trigger_from_dut_signal_name,
s_fiji_fault_detect_i => $fiji_fault_detection_signal_name,
s_fiji_original_i => $fiji_original_signal_name,
s_fiji_modified_o => $fiji_modified_signal_name
......
......@@ -546,42 +546,42 @@ sub update {
#
# show line & text if enabled
$self->itemconfigure($internal_reset_elements->{'line'}, -state => ($design_ref->{'RESET_DUT_OUT_EN'} == 1 || $design_ref->{'RESET_DUT_IN_EN'} == 1) ? "normal" : "hidden");
$self->itemconfigure($internal_reset_elements->{'line'}, -state => ($design_ref->{'RST_DUT_OUT_EN'} == 1 || $design_ref->{'RST_DUT_IN_EN'} == 1) ? "normal" : "hidden");
$self->itemconfigure($internal_reset_elements->{'text'}, -state => ($design_ref->{'RESET_DUT_OUT_EN'} == 1 || $design_ref->{'RESET_DUT_IN_EN'} == 1) ? "normal" : "hidden");
$self->itemconfigure($internal_reset_elements->{'text'}, -state => ($design_ref->{'RST_DUT_OUT_EN'} == 1 || $design_ref->{'RST_DUT_IN_EN'} == 1) ? "normal" : "hidden");
# decide arrow direction if inverting
$self->itemconfigure(
$internal_reset_elements->{'line'}, -arrow => ($design_ref->{'RESET_DUT_OUT_EN'} && $design_ref->{'RESET_DUT_OUT_ACTIVE'} == 0)