Commit 4028b9a1 authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

Added Fault Detection Signal invert mask,

cleanup
parent 10ced921
......@@ -35,6 +35,7 @@ use work.public_config_pkg.c_reset_ext_active;
use work.public_config_pkg.c_reset_dut_out_active;
use work.public_config_pkg.c_baudrate;
use work.public_config_pkg.c_frequency;
use work.public_config_pkg.c_fault_detect_invert_mask;
use work.private_config_pkg.c_pattern_bits;
use work.private_config_pkg.c_tx_buffer_depth;
......
......@@ -19,7 +19,7 @@
architecture struc of fault_injection_top is
signal s_fiu_connector : std_logic_vector(c_fiu_config'length-1 downto 0); -- connects FIUs
signal s_fiu_connector : std_logic_vector(c_fiu_config'length-1 downto 0); -- connects FIUs' shift registers
signal s_reset_n : std_logic; -- internal low-active reset signal
......@@ -60,14 +60,15 @@ architecture struc of fault_injection_top is
begin -- architecture struc
-- do something with the fault detection data
s_fault_detect <= s_fiji_fault_detect_i(1 downto 0);
-- feed data to FIUs
s_fault_detect <= s_fiji_fault_detect_i(1 downto 0) xor c_fault_detect_invert_mask;
-- multiplex reset
s_reset_n <= '0' when s_fiji_reset_ext_i = c_reset_ext_active or
s_fiji_reset_dut_out_i = c_reset_dut_out_active else '1';
-- instantiate FIUs according to config by Generics
-- instantiate FIUs according to config
-- connect FIUs' shift registers from low to high
-- i.e. shift data in through FIU0
generate_FIUs : for i in c_fiu_config'length-1 downto 0 generate
generate_FIUs_greater_0 : if i > 0 generate
......@@ -175,7 +176,10 @@ begin -- architecture struc
s_buffer_rdrq <= '1' when s_tx_state = READ_BUFFER else '0';
s_uart_send_msg <= '1' when s_tx_state = SEND_MESSAGE else '0';
-- sequencing message sending and reading from fifo
-- purpose: sequencing message sending and reading from fifo
-- type : sequential
-- inputs : s_fiji_clk_i, s_reset_n,s_tx_ready,s_buffer_empty
-- outputs: s_tx_state
p_reader : process(s_fiji_clk_i, s_reset_n)
begin
if s_reset_n = '0' then
......
......@@ -15,8 +15,10 @@
-- --
-- Description: --
-- Fault injection transmit buffer architecture file --
-- Implements a circular buffer using registers.
-- Keeping track of the empty/full status is implemented using the
-- Implements a circular buffer using registers. --
-- Keeping track of the empty/full status is implemented using an extra bit --
-- in the read/write pointer (i.e. by counting and comparing the number of --
-- wraps of the pointers modulo 2)
--------------------------------------------------------------------------------
architecture rtl of fault_injection_tx_buffer is
......
......@@ -43,6 +43,8 @@ begin -- architecture rtl
-- pragma synthesis_off
-- purpose: report baude rate parameters for simulation
-- type : unsynthesizable
p_report_bauderror : process is
begin
report "[fault_injection_uart:p_report_bauderror] Baud rate counter selected clock freq.: "&integer'image(
......@@ -58,7 +60,7 @@ begin -- architecture rtl
-- purpose: synchronizes RX data to system clock
-- type : sequential
-- inputs : s_clk_i, s_reset_n_i, s_rx_i
-- outputs: s_rx_sync
-- outputs: s_rx_sampled
p_rx_sync : process (s_clk_i, s_reset_n_i) is
begin -- process p_rx_sync
if s_reset_n_i = '0' then -- asynchronous reset (active low)
......@@ -72,7 +74,7 @@ begin -- architecture rtl
-- purpose: receives bits
-- type : sequential
-- inputs : s_clk_i, s_reset_n_i, s_sample_enable, s_rx_sampled
-- outputs:
-- outputs: s_data_o, s_data_valid_o, s_uart_error_o, s_byte_start_o
p_receiver : process (s_clk_i, s_reset_n_i) is
begin -- process p_receiver
if s_reset_n_i = '0' then -- asynchronous reset (active low)
......@@ -89,15 +91,14 @@ begin -- architecture rtl
s_data_valid_o <= '0';
s_byte_start_o <= '0';
case s_receiver_state is
when WAIT_START =>
-- Wait for a START bit to occurr (transition from MARK -> SPACE level)
when WAIT_START => -- Wait for a START bit to occurr
s_uart_error_o <= '0';
if s_rx_sampled(3 downto 1) = "100" then
-- (transition from MARK -> SPACE level)
s_receiver_state <= WAIT_OFFSET;
s_receiver_count <= to_unsigned(c_num_clock_cycles/2, s_receiver_count'length);
end if;
when WAIT_OFFSET =>
-- Wait for half a bit
when WAIT_OFFSET => -- Wait for half a bit
s_receiver_count <= s_receiver_count - 1;
if s_receiver_count = 0 then
......@@ -114,7 +115,7 @@ begin -- architecture rtl
end if;
when RECEIVE =>
when RECEIVE => -- receive 8 bits
s_receiver_count <= s_receiver_count - 1;
-- process the last 3 samples around the middle of a Bit
......@@ -148,7 +149,7 @@ begin -- architecture rtl
end if;
end if;
when WAIT_STOP =>
when WAIT_STOP => -- wait for the STOP bit
s_receiver_count <= s_receiver_count - 1;
if s_receiver_count = 0 then
......@@ -158,7 +159,7 @@ begin -- architecture rtl
s_uart_error_o <= '1';
report "[fault_injection_uart:p_receiver] Stop Bit Error ocurred. Stop Bit was not '1'." severity error;
end if;
-- go to receive next Byte
-- ready to receive next Byte
s_receiver_state <= WAIT_START;
end if;
when others =>
......@@ -188,8 +189,7 @@ begin -- architecture rtl
elsif s_clk_i'event and s_clk_i = '1' then -- rising clock edge
case s_transmitter_state is
when IDLE =>
-- wait for being enabled by external request
when IDLE => -- wait for being enabled by external request
s_parity <= '0';
-- update internal storage register
s_data_storage <= s_tx_data_i;
......@@ -199,8 +199,7 @@ begin -- architecture rtl
if s_tx_enable_i = '1' then
s_transmitter_state <= START;
end if;
when START =>
-- generate start bit
when START => -- generate start bit
-- reset transmitter bit counter
s_bit_count_tx <= to_unsigned(7, s_bit_count_tx'length);
......@@ -215,8 +214,8 @@ begin -- architecture rtl
s_transmitter_count <= to_unsigned(c_num_clock_cycles-1, s_transmitter_count'length);
s_transmitter_state <= DATA;
end if;
when DATA =>
-- set TX line
when DATA => -- transmit 8 bits
if s_bit_count_tx = 0 then
s_tx <= s_parity;
else
......@@ -240,8 +239,7 @@ begin -- architecture rtl
s_transmitter_state <= STOP;
end if;
end if;
when STOP =>
-- generate the STOP bit - 1 stop bit
when STOP => -- generate 1 STOP bit
-- generate the STOP bit as MARK
s_tx <= '1';
......
......@@ -40,7 +40,7 @@ begin -- architecture rtl
-- generate last bit output
s_data_o <= s_fault_shift(0)(0);
-- purpose: generate shift register
-- purpose: shift register for fault patterns
-- type : sequential
-- inputs : s_clk_i, s_reset_n_i, s_data_i
-- outputs: s_fault_shift, s_fault_select
......@@ -53,10 +53,14 @@ begin -- architecture rtl
if s_shift_enable_i = '1' then
l_shift_bits : for i in private_config_pkg.c_num_patterns-1 downto 0 loop
if i = private_config_pkg.c_num_patterns-1 then
-- shift in the pattern bits through highest pattern register
s_fault_shift(i)(private_config_pkg.c_num_select_bits-1) <= s_data_i;
else
-- the patterns are connected from the lowest bit of pattern n+1
-- to the highest bit of pattern n
s_fault_shift(i)(private_config_pkg.c_num_select_bits-1) <= s_fault_shift(i+1)(0);
end if;
-- shift the bits already in the pattern registers left
s_fault_shift(i)(private_config_pkg.c_num_select_bits-2 downto 0) <= s_fault_shift(i)(private_config_pkg.c_num_select_bits-1 downto 1);
end loop;
end if;
......@@ -77,11 +81,10 @@ begin -- architecture rtl
s_stuck_at_0 <= '0';
s_stuck_at_1 <= '1';
-- purpose: and together bits in the lfsr, store in stuck-at-open register
-- purpose: AND together bits in the lfsr, store in stuck-at-open register
-- type : sequential
-- inputs : s_clk_i, reset_n_i, s_lfsr_i
-- outputs: s_stuck_open
......@@ -98,11 +101,11 @@ begin -- architecture rtl
end if;
end process p_stuck_open;
-- invert the original signal for one cycle when fault is activated
s_seu <= not(s_original_i) when s_injection_start_i = '1' else s_original_i;
-- purpose: sequential logic for fault models
-- purpose: delay original signal for one cycle
-- type : sequential
-- inputs : s_clk_i, reset_n_i, s_original_i, s_injection_start_i
-- outputs: s_delay
......@@ -120,9 +123,13 @@ begin -- architecture rtl
-- Generate injected value
-----------------------------------------------------------------------------
-- if selectable at runtime
-- if faults are selectable at runtime
gen_all_fault_models : if g_fault_model = RUNTIME generate
-- purpose: multiplex between fault-free and fault models
-- type : combinational
-- inputs : s_fault_select, s_stuck_at_0, s_stuck_at_1, s_delay, s_seu, s_stuck_open, s_original_i
-- outputs: s_injected
p_sel : process (s_fault_select, s_stuck_at_0, s_stuck_at_1, s_delay, s_seu, s_stuck_open, s_original_i)
begin
case s_fault_select is
......@@ -136,6 +143,8 @@ begin -- architecture rtl
end process p_sel;
-- pragma translate off
-- purpose: report selected fault model for simulation
-- type : unsynthesizable
p_report_config : process
begin
wait until s_injection_start_i = '1';
......@@ -159,7 +168,7 @@ begin -- architecture rtl
end generate gen_all_fault_models;
------------------------------------------------------------------------------
-- if only one shall be generated
-- if only one fault model shall be generated
gen_only_stuck_at_0 : if g_fault_model = STUCK_AT_0 generate
s_injected <= s_stuck_at_0 when s_fault_select = c_fault_select_stuck_at_0 else
......@@ -191,7 +200,7 @@ begin -- architecture rtl
end generate gen_only_pass_thru;
-----------------------------------------------------------------------------
-- Multiplex injection
-- Generate output
-----------------------------------------------------------------------------
s_modified_o <= s_injected;
......
......@@ -57,6 +57,7 @@ proc build_config_pkg_from_cfg {global_pkg_file_name cfg_file_name} {
set TIMER_WIDTH 32
set BAUDRATE 115200
set FIU_NUM 0
set FAULT_DETECT_INVERT_MASK 0
if { [dict exists $cfgdict "CONSTS"] } {
set consts [dict get $cfgdict "CONSTS"]
......@@ -73,6 +74,9 @@ proc build_config_pkg_from_cfg {global_pkg_file_name cfg_file_name} {
if { [catch { set FIU_NUM [dict get $consts "FIU_NUM"] } ] } {
echo "Could not retrieve FIU_NUM from CONSTS section"
}
if { [catch { set FAULT_DETECT_INVERT_MASK [dict get $consts "FAULT_DETECT_INVERT_MASK"] } ] } {
echo "Could not retrieve FAULT_DETECT_INVERT_MASK from CONSTS section"
}
} else {
echo "Invalid config file: no CONSTS section."
......@@ -110,13 +114,13 @@ proc build_config_pkg_from_cfg {global_pkg_file_name cfg_file_name} {
}
set id [build_global_cfg_pkg $global_pkg_file_name $TIMER_WIDTH $FREQUENCY $BAUDRATE $fiu_list]
set id [build_global_cfg_pkg $global_pkg_file_name $TIMER_WIDTH $FREQUENCY $BAUDRATE $FAULT_DETECT_INVERT_MASK $fiu_list]
return $id
}
proc build_global_cfg_pkg {file_name timer_width fclk baud fiu_list} {
proc build_global_cfg_pkg {file_name timer_width fclk baud fault_detect fiu_list} {
if {[expr {[llength $fiu_list] % 2}] != 0} {
echo "Invalid# args in list"
......@@ -129,6 +133,8 @@ proc build_global_cfg_pkg {file_name timer_width fclk baud fiu_list} {
set ext_active 0
set int_active 1
set reset_dut_in_duration 4
set fault_detect_1 [expr {(($fault_detect >> 1) & 1)}]
set fault_detect_0 [expr {(($fault_detect) & 1)}]
# ID caluclation mechanism:
# proposal is to do this by taking the MD5 hash of all configuration values
......@@ -164,6 +170,8 @@ package public_config_pkg is
constant c_frequency : positive := $fclk;
-- The baud rate
constant c_baudrate : positive := $baud;
-- The invert mask for the fault detection signals
constant c_fault_detect_invert_mask : std_logic_vector(1 downto 0) := \"${fault_detect_1}${fault_detect_0}\";
------------------------------------------------------------------------------
-- LFSR configuration
......
......@@ -39,6 +39,7 @@ BAUDRATE=3000000
FIU_NUM=8
FIU_CFG_BITS=3
FREQUENCY=50000000
FAULT_DETECT_INVERT_MASK=2
[FIU0]
LFSR_MASK=1234
......
......@@ -9,6 +9,7 @@ add wave -noupdate /fault_injection_top_tb/DUT/s_fiji_rx_i
add wave -noupdate /fault_injection_top_tb/DUT/s_fiji_trigger_ext_i
add wave -noupdate /fault_injection_top_tb/DUT/s_fiji_trigger_dut_i
add wave -noupdate /fault_injection_top_tb/DUT/s_fiji_original_i
add wave -noupdate /fault_injection_top_tb/s_fiji_fault_detect_i
add wave -noupdate -divider Outputs
add wave -noupdate /fault_injection_top_tb/DUT/s_fiji_tx_o
add wave -noupdate /fault_injection_top_tb/DUT/s_fiji_reset_dut_in_o
......@@ -72,7 +73,7 @@ add wave -noupdate /fault_injection_top_tb/DUT/s_buffer_rdrq
add wave -noupdate /fault_injection_top_tb/DUT/generate_FIUs(7)/generate_FIUs_greater_0/i_fault_injection_unit/g_lfsr_mask
add wave -noupdate /fault_injection_top_tb/DUT/generate_FIUs(7)/generate_FIUs_greater_0/i_fault_injection_unit/s_stuck_open
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {9185660 ns} 1} {{Cursor 3} {0 ns} 0}
WaveRestoreCursors {{Cursor 1} {9185660000 ps} 1} {{Cursor 3} {0 ps} 0}
quietly wave cursor active 2
configure wave -namecolwidth 759
configure wave -valuecolwidth 344
......@@ -88,4 +89,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits us
update
WaveRestoreZoom {0 ns} {1428961 ns}
WaveRestoreZoom {0 ps} {3150 us}
......@@ -17,11 +17,12 @@
-- Default public config package for testbenches --
--------------------------------------------------------------------------------
-- Automatically generated Thu May 21 11:00:13 2015
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
library work;
use work.fault_selection_type_pkg.all;
use work.fault_selection_type_pkg.all;
package public_config_pkg is
......@@ -32,6 +33,8 @@ package public_config_pkg is
constant c_frequency : positive := 200000000;
-- The baud rate
constant c_baudrate : positive := 3000000;
-- The invert mask for the fault detection signals
constant c_fault_detect_invert_mask : std_logic_vector(1 downto 0) := "10";
------------------------------------------------------------------------------
-- LFSR configuration
......@@ -49,12 +52,12 @@ package public_config_pkg is
------------------------------------------------------------------------------
-- Width of the timers in bytes.
constant c_timer_width : natural := 4;
constant c_timer_width : natural := 4;
-- FIC -> DUT reset signal: active level
constant c_reset_dut_in_active : std_logic := '0';
constant c_reset_dut_in_active : std_logic := '0';
-- reset duration
constant c_reset_dut_in_duration : positive := 4;
constant c_reset_dut_in_duration : positive := 4;
-- external reset signal: active level
constant c_reset_ext_active : std_logic := '0';
......@@ -64,11 +67,11 @@ package public_config_pkg is
-- active level of the external and internal triggers
constant c_trigger_ext_active : std_logic := '0';
constant c_trigger_dut_active : std_logic := '1';
constant c_trigger_ext_active : std_logic := '0';
constant c_trigger_dut_active : std_logic := '1';
-- hardware id
constant c_id : std_logic_vector(15 downto 0) := X"0123";
constant c_id : std_logic_vector(15 downto 0) := X"0123";
......@@ -78,38 +81,38 @@ package public_config_pkg is
------------------------------------------------------------------------------
type t_single_fiu_record is record
fault_model : t_select_fault_models; --Select dynamic or single fault model. See fault_injection_unit
lfsr_mask : std_logic_vector(c_lfsr_width-1 downto 0); -- Select which LFSR bits to AND with FIU enable
fault_model : t_select_fault_models; --Select dynamic or single fault model. See fault_injection_unit
lfsr_mask : std_logic_vector(c_lfsr_width-1 downto 0); -- Select which LFSR bits to AND for Stuck-Open
end record t_single_fiu_record;
type t_fiu_records is array (natural range <>) of t_single_fiu_record;
constant c_fiu_config : t_fiu_records := (
(fault_model => RUNTIME,
lfsr_mask => X"04D2"),
(fault_model => RUNTIME,
lfsr_mask => X"04D2"),
(fault_model => STUCK_AT_0,
lfsr_mask => X"0000"),
(fault_model => STUCK_AT_0,
lfsr_mask => X"0000"),
(fault_model => STUCK_AT_1,
lfsr_mask => X"0000"),
(fault_model => STUCK_AT_1,
lfsr_mask => X"0000"),
(fault_model => DELAY,
lfsr_mask => X"0000"),
(fault_model => DELAY,
lfsr_mask => X"0000"),
(fault_model => SEU,
lfsr_mask => X"0000"),
(fault_model => SEU,
lfsr_mask => X"0000"),
(fault_model => STUCK_OPEN,
lfsr_mask => X"0001"),
(fault_model => STUCK_OPEN,
lfsr_mask => X"0001"),
(fault_model => PASS_THRU,
lfsr_mask => X"0000"),
(fault_model => PASS_THRU,
lfsr_mask => X"0000"),
(fault_model => RUNTIME,
lfsr_mask => X"8001")
(fault_model => RUNTIME,
lfsr_mask => X"8001")
);
);
end package public_config_pkg;
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