Commit 3facaa95 authored by Stefan Tauner's avatar Stefan Tauner
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user manual: add DUT abbreviation

parent 0d0a6337
\acro{FIJI}{Fault InJection Instrumenter}
\acro{DUT}{Design Under Test}
\acro{FIC}{Fault Injection Controller}
\acro{FIJI}{Fault InJection Instrumenter}
\acro{FIU}{Fault Injection Unit}
\acro{VQM}{Verilog Quartus Mapping}
\acro{VM}{Verilog Mapping}
\acro{LFSR}{Linear Feedback Shift Register}
\acro{VM}{Verilog Mapping}
\acro{VQM}{Verilog Quartus Mapping}
\section{Introduction}
%Silence bibtex error \cite{adams2007hitchhiker}
The \ac{FIJI} suite provides a tool flow for
performing fault injection tests on chip designs in an FPGA-based environment.
......@@ -10,10 +9,10 @@ carried out with the help of partial reconfiguration, \ac{FIJI} is relatively
technology-independent as no knowledge about the bitstream format and
the mapping to configuration frames within the FPGA device is required.
An overview of the \ac{FIJI} tool flow is shown in Figure~\ref{fig:fijiflow}.
Data and actions framed in red have to be supplied by the user.
An overview of the \ac{FIJI} tool flow is shown in Figure~\ref{fig:fijiflow} and explained below.
Data and actions framed in red in the picture have to be supplied by the user.
\ac{FIJI} works by instrumenting a given netlist of a design under test with
\ac{FIJI} works by instrumenting a given netlist of a \ac{DUT} with
fault injection logic according to a predefined fault injection configuration.
A parametrized \ac{FIC} hardware module is added outside
of the original design. The generation of the fault injection configuration
......
......@@ -77,7 +77,7 @@ configuration:
\item \underline{Clock Settings}
The \textit{\ac{FIJI}} fault injection logic is clocked from the
clock of the clock domain in the DUT where faults are injected.
clock of the clock domain in the \ac{DUT} where faults are injected.
The name and frequency of this clock net need to be specified.
\item \underline{LFSR Settings}
......@@ -96,26 +96,26 @@ configuration:
pin. This feature can be turned on and off in this tab.
If an external reset pin is desired, the polarity and name must be entered.
\item \underline{Reset from DUT to \ac{FIJI}}
\item \underline{Reset from \acs{DUT} to \ac{FIJI}}
In addition to the external reset via pin, also any net of the
DUT can be used to reset the \ac{FIJI} logic. This feature can be
\ac{DUT} can be used to reset the \ac{FIJI} logic. This feature can be
turned on and off in this tab. If an internal reset from the
DUT is desired, the polarity and source net name must be entered.
When the \textit{Reset from DUT to \ac{FIJI}} feature is used, the
\textit{Reset from \ac{FIJI} to DUT} feature cannot be used at the
\ac{DUT} is desired, the polarity and source net name must be entered.
When the \textit{Reset from \ac{DUT} to \ac{FIJI}} feature is used, the
\textit{Reset from \ac{FIJI} to \ac{DUT}} feature cannot be used at the
same time.
If both the external reset feature and the reset from DUT to
If both the external reset feature and the reset from \ac{DUT} to
\ac{FIJI} are enabled, the reset sources are ORed together and used
as the \ac{FIJI} logic's asynchronous reset signal.
\item \underline{Reset from \ac{FIJI} to DUT}
\item \underline{Reset from \ac{FIJI} to \acs{DUT}}
In contrast to the feature described above, the \ac{FIJI} logic can
also be used as a source for a reset net in the DUT.
When the \textit{Reset from \ac{FIJI} to DUT} feature is used, the
\textit{Reset from DUT to \ac{FIJI}} feature cannot be used at the
same time. If an internal reset from \ac{FIJI} to the DUT is desired,
also be used as a source for a reset net in the \ac{DUT}.
When the \textit{Reset from \ac{FIJI} to \acs{DUT}} feature is used, the
\textit{Reset from \acs{DUT} to \ac{FIJI}} feature cannot be used at the
same time. If an internal reset from \ac{FIJI} to the \ac{DUT} is desired,
the polarity, target net name, and desired reset pulse duration
must be entered.
......@@ -125,7 +125,7 @@ configuration:
events external to \ac{FIJI}, trigger signals can be used to
continue a suspended test execution.
Both an external trigger via an FPGA pin as well as an internal
trigger using a net in the DUT as a source can be used. The
trigger using a net in the \ac{DUT} as a source can be used. The
\ac{FIJI} logic can be instructed at runtime if it shall wait for
the internal or external trigger signal.
For both the internal and the external trigger facilities,
......@@ -133,7 +133,7 @@ configuration:
\item \underline{Fault Detection Settings}
The value of up to two nets in the DUT can be communicated back to the
The value of up to two nets in the \ac{DUT} can be communicated back to the
host as a means for fault detection. The names and \textit{error}
levels of these nets need to be specified when they are used.
......@@ -215,7 +215,7 @@ nets are selected using this method.
\end{figure}
Once a net is selected, \textit{\ac{FIJI} Setup} checks if this net is actually
present in the DUT netlist. The user must then select the driver for
present in the \ac{DUT} netlist. The user must then select the driver for
this net using the \textit{Driver} button (3). This opens up a dialog
with all possible driver objects for this net prompting the user to select
one of these options.
......
......@@ -4,7 +4,7 @@ The \textit{\ac{FIJI} Instrumentation} tool reads in the original Verilog
netlist and the configuration file edited using the \textit{\ac{FIJI} Setup}
tool.
Its main task is to actually perform the modifications of the DUT netlist
Its main task is to actually perform the modifications of the \ac{DUT} netlist
specified in the \ac{FIJI} configuration file. For each \textit{[\acs{FIU}$n$]} entry
in this file, it breaks up the corresponding net in an \textit{original}
and a \textit{modified} net, routes these nets to the toplevel, and creates
......@@ -38,7 +38,7 @@ the following parameters and switches:
Changes the filename prefix for all generated files.
\textit{This parameter is optional.} If it is not specified, the module
name of the toplevel in the DUT netlist used.
name of the toplevel in the \ac{DUT} netlist used.
\item \texttt{-o, {-}{-}output-dir=<path>}
......
......@@ -13,7 +13,7 @@ FPGA implementation. To that end, the following steps have to be observed:
device for which the original netlist was generated
\item Add as source files:
\begin{itemize}
\item The modified DUT netlist
\item The modified \ac{DUT} netlist
\item The generated VHDL file containing the configuration package
\item The generated VHDL file containing the wrapper entity
\item The VHDL sources of the fault injection logic (located in \texttt{\$FIJI\_ROOT/hw/rtl/})
......@@ -21,12 +21,12 @@ FPGA implementation. To that end, the following steps have to be observed:
\item Set the name of the wrapper entity as top-level entity
\item Add any \textit{synthesis} constraint files existing from the
original synthesis project and adapt paths to HDL modules in the
DUT as necessary (one layer of hierarchy will be added as the
\ac{DUT} as necessary (one layer of hierarchy will be added as the
module is instantiated by the wrapper VHDL entity)
\item Optionally, add the \textit{synthesis} constraints file generated
by the \textit{\ac{FIJI} Instrumentation} tool. The constraints in
this file attempt to enforce the cross-hierarchy optimization
level between the fault injection logic and the generated DUT
level between the fault injection logic and the generated \ac{DUT}
netlist (See \ref{sec:preventing_optimizations})
\item Optionally, add any additional \textit{synthesis} constraints
\end{enumerate}
......@@ -35,8 +35,8 @@ FPGA implementation. To that end, the following steps have to be observed:
\label{sec:preventing_optimizations}
It may be desirable to prevent cross-hierarchy optimization between the
fault injection logic and the modified DUT netlist, e.g. to prevent further
modification of the already verified DUT netlist or to preserve existing
fault injection logic and the modified \ac{DUT} netlist, e.g. to prevent further
modification of the already verified \ac{DUT} netlist or to preserve existing
constraints for parts of the original netlist.
Synopsys' \textit{Synplify Pro} offers the possibility to define \textit{Compile
......@@ -44,13 +44,13 @@ Points} which correspond to modules in a HDL design \cite{synpmanual}. At the st
compilation process, Synplify checks if the source for each compile point
has changed since the last compilation. Only compile points whose source
has changed are resynthesized.
Thus, to prevent cross-boundary optimization and resynthesis of the DUT netlist,
a compile point has to be defined for the instantiated DUT.
Thus, to prevent cross-boundary optimization and resynthesis of the \ac{DUT} netlist,
a compile point has to be defined for the instantiated \ac{DUT}.
To do this via the Synplify GUI, the following steps have to be observed:
\begin{enumerate}
\item Create the project and implementation, and add all source files
including the DUT netlist
including the \ac{DUT} netlist
\item Synplify needs to parse the design's hierarchy. Thus, perform
\textit{Compile only} \keystroke{F7}.
\item Afterwards, open the SCOPE constraints editor (e.g., be double-clicking
......@@ -70,8 +70,8 @@ the following constraint:
define_compile_point {v:[<library>].<DUT toplevel entity name>} -type {locked}
\end{verbatim}
The \textit{library} string point to the library where the DUT can be
found. It can be omitted if the DUT is compiled into the \texttt{work} library.
The \textit{library} string point to the library where the \ac{DUT} can be
found. It can be omitted if the \ac{DUT} is compiled into the \texttt{work} library.
\subsubsection{Constraints Export}
......@@ -81,7 +81,7 @@ When the \textit{Optimizations} setting in the \textit{\ac{FIJI} Setup} tool
\textit{\ac{FIJI} Instrument} generates an ``.fdc'' template constraints file for Synplify.
This file contains the necessary constraints to prevent cross-boundary optimization
between the fault injection logic and the logic in the DUT netlist. In order to
between the fault injection logic and the logic in the \ac{DUT} netlist. In order to
use the constraints contained in this file, it needs to be added as a source
file to the Synplify project and activated in the ``Implementation Options``.
......@@ -91,7 +91,7 @@ The file is written to the output directory, where also the instrumented netlist
\label{sec:place_and_route}
The synthesis process described in Section~\ref{sec:Synthesis} results in
one or more netlist files implementing the instrumented DUT and the fault
one or more netlist files implementing the instrumented \ac{DUT} and the fault
injection logic. These netlist files must now be placed and routed using
an FPGA vendor's P\&R tool.
......@@ -119,7 +119,7 @@ of P\&R tools:
\subsubsection{Fixing Physical Placement Manually}
\label{sec:fixing_physical_placement}
It may be desired to fix the physical location of the DUT netlist, so
It may be desired to fix the physical location of the \ac{DUT} netlist, so
that the mapping to specific logic elements is unchanged even if the
fault injection logic is modified. This can be useful in the following
cases:
......@@ -151,7 +151,7 @@ perform the following steps in the Quartus GUI:
\item In the \textit{Project Navigator}, select the \textit{Hierarchy Browser}
tab
\item Unfold the top level entity in the tree view
\item Right-click on the top-level entity of the DUT netlist (\texttt{i\_DUT})
\item Right-click on the top-level entity of the \ac{DUT} netlist (\texttt{i\_DUT})
\item In the context menu, navigate to \textit{LogicLock Region} and
select \textit{Create new LogicLock Region}
\item A new \textit{floating} region for placement is created.
......@@ -187,7 +187,7 @@ perform the following steps in the Vivado GUI:
synthesis process) as a source file.
\item Open the \textit{Synthesized Design} perspective.
\item In the \textit{Netlist} tab, right-click on the top-level entity
if the DUT netlist (\texttt{i\_DUT})
if the \ac{DUT} netlist (\texttt{i\_DUT})
\item In the context menu, navigate to \textit{Floorplanning} and
select \textit{New Pblock}. A Pblock is Xilinx Vivado's equivalent
to a \textit{LogicLock Region}.
......@@ -221,7 +221,7 @@ When the \textit{Optimizations} setting in the \textit{\ac{FIJI} Setup} tool
the selected P\&R tool (``.qsf'' for Altera Quartus, ``.xdc'' for Xilinx Vivado).
These files contain the necessary directives to set up a physical partition for the
DUT entity. They can either be imported into the P\&R tool directly or copied
\ac{DUT} entity. They can either be imported into the P\&R tool directly or copied
manually to a central constraints file.
The files are written to the output directory, where also the instrumented netlist file is placed.
......
\section{Runtime Fault Injection}
\section{Run-time Control of Fault Injection}
\label{sec:runtime}
\subsection{Command-line Tool}
......@@ -152,7 +152,7 @@ Following the time durations, the trigger mode must be selected, where
external trigger (\texttt{1}) shall be used.
Finally, the user has to enter if the fault injection logic shall apply
a reset to the DUT before applying this fault injection pattern.
a reset to the \ac{DUT} before applying this fault injection pattern.
Informations other than the fault patterns (e.g., the serial port,
baud rate, or \texttt{HOLD\_ON\_FAULT\_DETECT} information) are read from
......@@ -247,7 +247,7 @@ reset options are disabled.
Additionally, parameters for the test execution itself can be set: If the
sequence is to be repeated once completed, and after which pattern the repetion
should start again (this is particularly useful if the first pattern is
used to reset the DUT), and under which circumstances to halt test execution.
used to reset the \ac{DUT}), and under which circumstances to halt test execution.
In addition to these configurable halting conditions, test execution is
always stopped when an ID or CRC error is encountered.
......@@ -267,7 +267,7 @@ logic is ready.
As can also be seen in the Figure, the
hardware configuration information from the \textit{\ac{FIJI} Settings} file
is incorporated in this view. In the hardware configuration for loaded
in the screenshot, the \acs{FIJI}-to-DUT reset feature was turned off, and
in the screenshot, the \acs{FIJI}-to-\acs{DUT} reset feature was turned off, and
\textit{\ac{FIJI} Download GUI} notifies the user by graying-out the respective
checkbox.
......@@ -291,8 +291,8 @@ are configurable:
that one fault configuration for one FIU does is \textit{NONE} (i.e., fault-free)
\item If it is possible that more than one FIU is configured fault in one
fault configuration via the (``multiple faults per pattern'')
\item If the FIJI-to-DUT reset signal shall be asserted in the initial
fault configuration (e.g., to bring the DUT into a defined state prior
\item If the FIJI-to-\acs{DUT} reset signal shall be asserted in the initial
fault configuration (e.g., to bring the \ac{DUT} into a defined state prior
to fault injection)
\end{itemize}
......
\section{FIJI Directory Structure}
\begin{figure}[ht]
\centering
\input{img/fiji_dirs}
\caption{\ac{FIJI} Directory Structure}
\label{fig:fijidir}
\end{figure}
\ No newline at end of file
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