Commit 3f1749ce authored by Stefan Tauner's avatar Stefan Tauner
Browse files

Port Netlist to refined Verilog-Perl API (PinSelection.pm)

parent dcf143c2
......@@ -321,7 +321,7 @@ sub _add_port_to_hierarchy {
$cell->new_pin(
name => $name,
portname => $np->name,
netnames => [{'netname' => $np->net->name}],
pinselects => [{'netname' => $np->net->name}],
);
# let verilog-perl find the net and port.
......@@ -558,24 +558,24 @@ sub instrument_net {
if (ref($connection) eq "Verilog::Netlist::Pin") {
# If the driver is a pin of a (sub)cell, connect this pin to the intermediate net
$logger->debug("Connecting (output) pin \"" . $connection->cell->name . HIERSEP . $connection->name . "\" to intermediate net \"$net_name_tmp\"");
for my $netname ($connection->netnames) {
if ($netname->{'netname'} eq $net->name) {
for my $pinselect ($connection->pinselects) {
if ($pinselect->netname eq $net->name) {
$driver = $connection;
$netname->{'netname'} = $net_name_tmp; # FIXME: do we need to force a re-link (by deleting $connection->nets)?
$pinselect->netname($net_name_tmp); # FIXME: do we need to force a re-link (by deleting $connection->nets)?
# The intermediate net is a vector if the underlying net is a bus and we do not just select a single bit
# This is the case if
# - the underlying net is a vector and the driver covers all indices (implicitly by having no msb/lsb set)
# - the underlying net is a vector and the driver covers some indices (by having two different indices set)
# Also, if we instrument a second bit of a vector we need to make sure this instrumentation is handled as if the
# the driver itself is a vector.
if (defined($net->msb) && (!defined($netname->{'msb'}) || ($netname->{'msb'} != $netname->{'lsb'}))) {
if (defined($net->msb) && (!defined($pinselect->msb) || ($pinselect->msb != $pinselect->lsb))) {
$driver_is_vector = 1;
} elsif (defined($net_tmp) && defined($net_tmp->userdata("first_instrumented_bit"))) {
$driver_is_vector = 1;
} else {
# Make sure we do not output the index unnecessarily (if the driver is a single bit of a vector)
undef($netname->{'msb'});
undef($netname->{'lsb'});
$pinselect->msb(undef);
$pinselect->lsb(undef);
}
}
}
......@@ -681,10 +681,10 @@ sub instrument_net {
# We also need to fix the previous assignment of the respective bit...
if (ref($prev_driver) eq "Verilog::Netlist::Pin") {
$logger->debug(" reassigning pin \"" . $prev_driver->name . "\": $net_name_tmp --> $net_name_tmp\[$prev_bit\]");
for my $netname ($prev_driver->netnames) {
if ($netname->{'netname'} eq $net_name_tmp) {
$netname->{'msb'} = $prev_bit;
$netname->{'lsb'} = $prev_bit;
for my $pinselect ($prev_driver->pinselects) {
if ($pinselect->netname eq $net_name_tmp) {
$pinselect->msb($prev_bit);
$pinselect->lsb($prev_bit);
last;
}
}
......@@ -1236,11 +1236,11 @@ sub _get_net_connections {
# FIXME: check for duplicates: nets can be present multiple times in a single pin declaration:
# in case of concatenations, e.g. .S({GND, GND, GND, some_wire}).
# These can never be drivers though in practice.
foreach my $netname ($pin->netnames) {
my $bit_offset_range = _offset_of_bit_in_range($bit, $netname->{'msb'}, $netname->{'lsb'});
if ($netname->{'netname'} eq $net_name && ($bit_offset_range != -1)) {
foreach my $pinselect ($pin->pinselects) {
my $bit_offset_range = _offset_of_bit_in_range($bit, $pinselect->msb, $pinselect->lsb);
if ($pinselect->netname eq $net_name && ($bit_offset_range != -1)) {
# Remember the bit's offset
if(defined($netname->{'msb'})) {
if(defined($pinselect->msb)) {
$pin->userdata('fiji_driver_bit' => $bit_offset_total + $bit_offset_range);
}
my $dir = (!defined($pin->port)) ? "unknown" : ($pin->port->direction eq 'in') ? "in" : "out";
......@@ -1261,8 +1261,8 @@ sub _get_net_connections {
}
}
$bit_offset_total++;
if (defined($netname->{'msb'})) {
my ($low, $high) = _extract_low_high($netname->{'lsb'}, $netname->{'msb'});
if (defined($pinselect->msb)) {
my ($low, $high) = _extract_low_high($pinselect->lsb, $pinselect->msb);
$bit_offset_total += $high - $low;
}
}
......
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