Commit 3b9e282b authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
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HX8K/Yosys Demo

parent 79d5350c
# HX8K Demo for FIJI+Yosys #
## Prerequisites ##
* Yosys, Arachne-PNR, icepack
* (sadly) Synplify as the VHDL frontend
* FIJI (+environment variable `$FIJI_ROOT` pointing to the checked-out FIJI directory)
* Configuration of Synplify in `impl/instrumented/Makefile`
## FIJI Flow ##
1. Carry out the initial synthesis step to obtain a netlist & configure
FIJI by executing
$ make fiji-instrument
in `impl/original`
2. Perform the second synthesis step by running
$ make prog && make fiji-launch
in `impl/instrumented`
3. Inject & observe faults using the FIJI EE GUI
## Non-FIJI Flow ##
To just implement & download the original hardware, just run
$ make prog
in `impl/original`
## Simulation ##
To simulate the design for a few frames, run
$ make
in `sim`. Not much automated checking done here...
; FIJI::ConfigSorted 0.1
; Wed Sep 13 15:57:41 2017
[CONSTS]
BAUDRATE=115200
CFGS_PER_MSG=2
CLOCK_NET="tinyvga/clk36m"
FD_1_EN=0
FD_1_INVERT=0
FD_1_NAME=""
FD_2_EN=0
FD_2_INVERT=0
FD_2_NAME=""
FIU_CFG_BITS=3
FIU_NUM=5
FREQUENCY=36000000
IMPL_TOOL=XILINX_VIVADO
INST_LOG=fiji_instrument.log
LFSR_POLY=0x2d
LFSR_SEED=0xcafe
LFSR_WIDTH=16
OPTIMIZATIONS=ALLOW
OUTPUT_DIR=.
RST_DUT_IN_ACT=1
RST_DUT_IN_DUR=1
RST_DUT_IN_EN=0
RST_DUT_IN_NAME=
RST_DUT_OUT_ACT=1
RST_DUT_OUT_EN=1
RST_DUT_OUT_NAME="tinyvga/reset"
RST_EXT_ACT=1
RST_EXT_EN=0
RST_EXT_IN_NAME=s_fiji_reset_i
RX_IN_NAME=s_fiji_rx_i
SYNTHESIS_TOOL=SYNPLIFY_PRO
TIMER_WIDTH=4
TRIG_DUT_ACT=1
TRIG_DUT_EN=0
TRIG_DUT_NAME=""
TRIG_EXT_ACT=1
TRIG_EXT_EN=0
TRIG_EXT_IN_NAME=s_fiji_trig_ext_i
TX_OUT_NAME=s_fiji_tx_o
[FIU0]
DRIVER_PATH="tinyvga/_535_/Q"
DRIVER_TYPE=PIN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x10
NAME=
NET_NAME="tinyvga/green[3]"
[FIU1]
DRIVER_PATH="tinyvga/_531_/Q"
DRIVER_TYPE=PIN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x20
NAME=
NET_NAME="tinyvga/red[3]"
[FIU2]
DRIVER_PATH="tinyvga/_539_/Q"
DRIVER_TYPE=PIN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x40
NAME=
NET_NAME="tinyvga/blue[3]"
[FIU3]
DRIVER_PATH="tinyvga/_544_/Q"
DRIVER_TYPE=PIN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x20
NAME=
NET_NAME="tinyvga/memcol_off[4]"
[FIU4]
DRIVER_PATH="tinyvga/_549_/Q"
DRIVER_TYPE=PIN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x40
NAME=
NET_NAME="tinyvga/memln_off[4]"
SOURCE=../fiji/tinyvga_instrumented.vm synp/hx8k/tinyvga_fiji.vm synplify_support_modules.v
SYNPLIFY=synplify_pro
SYNPFLAGS=-licensetype synplifypremierdp
.PHONY : all prog sta
all : tinyvga_fiji.bin
synp/hx8k/tinyvga_fiji.vm : ../fiji/tinyvga_wrapper.vhd ../fiji/tinyvga_config_pkg.vhd ../fiji/tinyvga_constraints.synplify.fdc
cd synp && $(SYNPLIFY) $(SYNPFLAGS) -batch -tcl synplify.tcl
tinyvga_fiji.blif : $(SOURCE)
yosys -v4 -l synth.log -p 'synth_ice40 -top fiji_top -blif $@; write_verilog -defparam tinyvga_fiji_netlist.v' -f verilog $(SOURCE)
tinyvga_fiji.asc: tinyvga_fiji.blif tinyvga_fiji.pcf
arachne-pnr -d 8k -o tinyvga_fiji.asc -p tinyvga_fiji.pcf tinyvga_fiji.blif -P ct256
sta : tinyvga_fiji.asc tinyvga_fiji.pcf
icetime -P ct256 -p tinyvga_fiji.pcf -o $@ -d hx8k -c 36 $<
tinyvga_fiji.bin: tinyvga_fiji.asc sta
icepack tinyvga_fiji.asc tinyvga_fiji.bin
prog : tinyvga_fiji.bin
iceprog tinyvga_fiji.bin
fiji-launch : ../fiji/tinyvga_download.cfg
$$FIJI_ROOT/bin/fiji_ee_gui.pl -s $<
history clear
project -new tinyvga_fiji.prj
impl -add hx8k
set_option -technology SBTiCE40
set_option -part iCE40HX8K
add_file tinyvga_fiji.prj
add_file ../../fiji/tinyvga_constraints.synplify.fdc
add_file -vhdl ../../fiji/tinyvga_wrapper.vhd
add_file -vhdl ../../fiji/tinyvga_config_pkg.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_controller_.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_controller_pkg.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_controller_rtl.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_top_.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_top_pkg.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_top_struc.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_tx_buffer_.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_tx_buffer_pkg.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_tx_buffer_rtl.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_uart_.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_uart_pkg.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_uart_rtl.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_unit_.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_unit_pkg.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_unit_rtl.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_selection_type_pkg.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/private_config_pkg.vhd
set_option -top_module fiji_top
set_option -result_file hx8k/tinyvga_fiji.edf
set_option -result_format edif
set_option -write_verilog 1
project -save tinyvga_fiji.prj
project -run
###==== BEGIN Header
# Synopsys, Inc. constraint file
# /home/fibich/git/vecs/fiji/fiji_public/docs/demos/tinyvga/impl/instrumented/synp/tinyvga_fiji.fdc
# Written on Wed Sep 13 15:39:05 2017
# by Synplify Pro, J-2014.09-SP2 FDC Constraint Editor
# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
# These sections are generated from SCOPE spreadsheet tabs.
###==== END Header
###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
###==== END Collections
###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
create_clock -name {s_fiji_clk} {n:s_fiji_clk} -period {28}
###==== END Clocks
###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
###==== END "Generated Clocks"
###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
###==== END Inputs/Outputs
###==== BEGIN Registers - (Populated from tab in SCOPE, do not edit)
###==== END Registers
###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
###==== END "Delay Paths"
###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
###==== END Attributes
###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
###==== END "I/O Standards"
###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
###==== END "Compile Points"
module VCC (output Y);
assign Y = 1'b1;
endmodule
module GND (output Y);
assign Y = 1'b0;
endmodule
set_io osc J3
set_io hsync P16
set_io vsync P15
set_io red[3] N16
set_io green[3] M15
set_io blue[3] M16
set_io red[2] L16
set_io green[2] K15
set_io blue[2] K16
set_io red[1] K14
set_io green[1] J14
set_io blue[1] G14
set_io red[0] F14
set_io green[0] J15
set_io blue[0] H14
set_io led[0] B5
set_io led[1] B4
set_io led[2] A2
set_io led[3] A1
set_io led[4] C5
set_io led[5] C4
set_io led[6] B3
set_io led[7] C3
set_io s_fiji_tx_o B12
set_io s_fiji_rx_i B10
SOURCE=../../rtl/tinyvga.v ../../rtl/pll_hx8k.v
.PHONY: sta all fiji-setup fiji-instrument
all : tinyvga.bin
tinyvga_netlist.v : tinyvga.blif
tinyvga.blif : $(SOURCE)
yosys -v4 -l synth.log -p 'synth_ice40 -top tinyvga -blif $@; write_verilog -defparam tinyvga_netlist.v' $^
tinyvga.asc: tinyvga.blif tinyvga.pcf
arachne-pnr -d 8k -o tinyvga.asc -p tinyvga.pcf tinyvga.blif -P ct256
sta : tinyvga.asc tinyvga.pcf
icetime -P ct256 -p tinyvga.pcf -o $@ -d hx8k -c 36 $<
tinyvga.bin: tinyvga.asc sta
icepack tinyvga.asc tinyvga.bin
prog : tinyvga.bin
iceprog tinyvga.bin
fiji-setup : ../fiji/fiji.cfg
fiji-instrument : ../fiji/tinyvga_download.cfg
../fiji/fiji.cfg : tinyvga_netlist.v | ../fiji
$(FIJI_ROOT)/bin/fiji_setup.pl -s $@ -n $<
../fiji/tinyvga_download.cfg : ../fiji/fiji.cfg tinyvga_netlist.v | ../fiji
$(FIJI_ROOT)/bin/fiji_instrument.pl -s ../fiji/fiji.cfg -n tinyvga_netlist.v -o ../fiji -p tinyvga
../fiji :
mkdir -p ../fiji
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set_io osc J3
set_io hsync P16
set_io vsync P15
set_io red[3] N16
set_io green[3] M15
set_io blue[3] M16
set_io red[2] L16
set_io green[2] K15
set_io blue[2] K16
set_io red[1] K14
set_io green[1] J14
set_io blue[1] G14
set_io red[0] F14
set_io green[0] J15
set_io blue[0] H14
set_io led[0] B5
set_io led[1] B4
set_io led[2] A2
set_io led[3] A1
set_io led[4] C5
set_io led[5] C4
set_io led[6] B3
set_io led[7] C3
/**
* PLL configuration
*
* This Verilog module was generated automatically
* using the icepll tool from the IceStorm project.
* Use at your own risk.
*
* Given input frequency: 12.000 MHz
* Requested output frequency: 36.000 MHz
* Achieved output frequency: 36.000 MHz
*/
module pll(
input clock_in,
output clock_out,
output locked
);
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0000), // DIVR = 0
.DIVF(7'b0101111), // DIVF = 47
.DIVQ(3'b100), // DIVQ = 4
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) uut (
.LOCK(locked),
.RESETB(1'b1),
.BYPASS(1'b0),
.REFERENCECLK(clock_in),
.PLLOUTCORE(clock_out)
);
endmodule
`default_nettype none
module tinyvga (input osc,
output reg [3:0] red,
output reg [3:0] green,
output reg [3:0] blue,
output reg [7:0] led,
output reg hsync,
output reg vsync);
wire clk36m;
wire reset;
wire locked;
reg [2:0] reset_sync;
// VGA
wire blank;
wire [10:0] column_next;
wire [9:0] line_next;
reg [9:0] column;
reg [9:0] line;
// Image mover
reg [5:0] sinetab [127:0];
reg [6:0] memcol;
reg [5:0] memcol_off;
reg [5:0] memln;
reg [5:0] memln_off;
reg [7:0] frame_cnt;
wire [7:0] frame_cnt_next;
////////////////////////////////////////////////////////////////////
pll pll_i(.clock_in(osc),.clock_out(clk36m),.locked(locked));
always @(posedge clk36m or negedge locked) begin
if (!locked)
reset_sync <= "111";
else
reset_sync <= {reset_sync[1:0],1'b0};
end
assign reset = reset_sync[2];
////////////////////////////////////////////////////////////////////
assign column_next = {1'b0, column} + 11'b1;
assign line_next = line + 10'b1;
assign blank = ((column_next > 800) || (line_next > 600));
assign frame_cnt_next = frame_cnt + 1;
always @(posedge clk36m) begin
if (reset) begin
column <= 10'b0;
line <= 10'b0;
hsync <= 1'b0;
vsync <= 1'b0;
memcol <= 7'h0;
memln <= 6'h0;
frame_cnt <= 8'b0;
led <= 8'b0;
end else begin
column <= column_next[9:0];
memcol <= column[7:1] + memcol_off;
memln <= line[6:1] + memln_off;
led <= frame_cnt;
if (column == 823)
hsync <= 1'b1;
else if (column == 895)
hsync <= 1'b0;
if (column_next[10]) begin
line <= line_next;
if (line == 601)
vsync <= 1'b1;
else if (line == 603)
vsync <= 1'b0;
else if (line == 624) begin
line <= 10'b0;
frame_cnt <= frame_cnt_next;
end
end
end
end
////////////////////////////////////////////////////////////////////
wire [6:0] sinetab_addr_a;
wire [6:0] sinetab_addr_b;
assign sinetab_addr_a = frame_cnt[6:0];
assign sinetab_addr_b = frame_cnt[6:0]+6'd32;
always @(posedge clk36m) begin
if (reset) begin
memln_off <= 0;
memcol_off <= 0;
end else begin
memln_off <= sinetab[sinetab_addr_a];
memcol_off <= sinetab[sinetab_addr_b];
end
end
initial
$readmemh("sinetab.mem",sinetab);
////////////////////////////////////////////////////////////////////
reg [11:0] imem [8191:0];
reg [11:0] memline;
initial
$readmemh("color.mem",imem);
always @(posedge clk36m) begin
if (reset) begin
red <= 4'b0;
green <= 4'b0;
blue <= 4'b0;
memline <= 12'b0;
end else begin
memline = imem[{memln,memcol}];