Commit 3b63575c authored by Stefan Tauner's avatar Stefan Tauner
Browse files

Fix two bus in Basys 3 Synplify project

 - The Basys 3 has non-inverted LEDs, thus we need to set the G_LED_ON
   generic.
 - The top_module needs to be set with the base name only.
 - Also, remove 2nd stage Synplify project.
parent 16fcb907
#-- Synopsys, Inc.
#-- Version J-2014.09-SP2
#-- Project file /home/fibich/git/vecs/fiji/fiji_public/docs/demos/tmr_vga/fiji/basys3_test_1/synp/spriteflyer_top.prj
#project files
add_file -fpga_constraint "spriteflyer_top.fdc"
add_file -vhdl -lib work "../fiji/tmr_vga_demo_config_pkg.vhd"
add_file -vhdl -lib work "../fiji/tmr_vga_demo_wrapper.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_controller_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_controller_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_controller_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_top_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_top_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_top_struc.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_tx_buffer_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_tx_buffer_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_tx_buffer_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_uart_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_uart_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_uart_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_unit_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_unit_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_unit_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_selection_type_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/private_config_pkg.vhd"
add_file -structver "../fiji/tmr_vga_demo_instrumented.vm"
add_file -fpga_constraint "../fiji/tmr_vga_demo_constraints.synplify.fdc"
#implementation: "basys3"
impl -add basys3 -type fpga
#
#implementation attributes
set_option -vlog_std sysv
set_option -project_relative_includes 1
#par_1 attributes
set_option -job par_1 -add par
#device options
set_option -technology Artix7
set_option -part XC7A35T
set_option -package CPG236
set_option -speed_grade -1
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
# mapper_options
set_option -frequency auto
set_option -write_verilog 1
set_option -write_vhdl 0
set_option -srs_instrumentation 1
# xilinx_options
set_option -RWCheckOnRam 1
# Xilinx Virtex2
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
# Xilinx Artix7
set_option -use_vivado 1
set_option -enable_prepacking 1
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "basys3/spriteflyer_top.vm"
impl -active "basys3"
......@@ -2,7 +2,7 @@
// Written by Synplify Pro
// Product Version "J-2014.09-SP2"
// Program "Synplify Pro", Mapper "maprc, Build 2453R"
// Tue Apr 11 12:32:33 2017
// Thu Apr 13 14:53:49 2017
//
// Source file index table:
// Object locations will have the form <file>:<line>
......@@ -193,34 +193,6 @@ wire NC4 ;
.C(s_clk_c),
.CLR(s_reset_x_i_c)
);
// @10:42
FDC \s_debounce_count_Z[0] (
.Q(s_debounce_count[0]),
.D(s_debounce_count_3[0]),
.C(s_clk_c),
.CLR(s_reset_x_i_c)
);
// @10:42
FDC \s_debounce_count_Z[1] (
.Q(s_debounce_count[1]),
.D(un2_s_debounce_count_1_cry_4_O[0]),
.C(s_clk_c),
.CLR(s_reset_x_i_c)
);
// @10:42
FDC \s_debounce_count_Z[2] (
.Q(s_debounce_count[2]),
.D(un2_s_debounce_count_1_cry_4_O[1]),
.C(s_clk_c),
.CLR(s_reset_x_i_c)
);
// @10:42
FDC \s_debounce_count_Z[3] (
.Q(s_debounce_count[3]),
.D(un2_s_debounce_count_1_cry_4_O[2]),
.C(s_clk_c),
.CLR(s_reset_x_i_c)
);
// @10:42
FDC \s_debounce_count_Z[4] (
.Q(s_debounce_count[4]),
......@@ -319,6 +291,34 @@ wire NC4 ;
.C(s_clk_c),
.CLR(s_reset_x_i_c)
);
// @10:42
FDC \s_debounce_count_Z[0] (
.Q(s_debounce_count[0]),
.D(s_debounce_count_3[0]),
.C(s_clk_c),
.CLR(s_reset_x_i_c)
);
// @10:42
FDC \s_debounce_count_Z[1] (
.Q(s_debounce_count[1]),
.D(un2_s_debounce_count_1_cry_4_O[0]),
.C(s_clk_c),
.CLR(s_reset_x_i_c)
);
// @10:42
FDC \s_debounce_count_Z[2] (
.Q(s_debounce_count[2]),
.D(un2_s_debounce_count_1_cry_4_O[1]),
.C(s_clk_c),
.CLR(s_reset_x_i_c)
);
// @10:42
FDC \s_debounce_count_Z[3] (
.Q(s_debounce_count[3]),
.D(un2_s_debounce_count_1_cry_4_O[2]),
.C(s_clk_c),
.CLR(s_reset_x_i_c)
);
// @10:46
LUT1 un2_s_debounce_count_1_axb_14_cZ (
.I0(s_debounce_count[14]),
......@@ -8602,7 +8602,7 @@ G_GREEN_WIDTH=4
G_BLUE_WIDTH=4
G_HSYNC_ACT="'0'"
G_VSYNC_ACT="'0'"
G_LED_ON="'0'"
G_LED_ON="'1'"
*/
input s_clk_i ;
input s_reset_x_i ;
......@@ -8626,6 +8626,7 @@ wire [8:0] s_blue_tmr_partitions;
wire [3:0] s_red_o_c;
wire [3:0] s_green_o_c;
wire [3:0] s_blue_o_c;
wire [3:1] s_ledg_o_c;
wire s_ce25 ;
wire s_tmr_en ;
wire s_blank ;
......@@ -8635,21 +8636,15 @@ wire s_green_err ;
wire s_blue_err ;
wire VCC ;
wire GND ;
wire s_blue_err_led ;
wire s_red_err_led ;
wire s_green_err_led ;
wire s_clk_c ;
wire s_reset_x_i_c ;
wire s_tmr_en_i_c ;
wire s_hsync_o_c ;
wire s_vsync_o_c ;
wire s_red_err_led_i ;
wire s_green_err_led_i ;
wire s_blue_err_led_i ;
wire un1_s_ledg_o_i ;
wire s_red_err_led_0 ;
wire s_green_err_led_0 ;
wire s_blue_err_led_0 ;
wire un1_s_ledg_o_lut6_2_O6 ;
wire s_red_err_led ;
wire s_green_err_led ;
wire s_blue_err_led ;
wire s_clk_i_ibuf_iso ;
GND GND_cZ (
.G(GND)
......@@ -8664,73 +8659,61 @@ wire s_clk_i_ibuf_iso ;
IBUFG s_clk_i_ibuf_iso_cZ (
.O(s_clk_i_ibuf_iso),
.I(s_clk_i)
);
INV \s_ledg_o_obuf_RNO[1] (
.I(s_blue_err_led),
.O(s_blue_err_led_i)
);
INV \s_ledg_o_obuf_RNO[2] (
.I(s_green_err_led),
.O(s_green_err_led_i)
);
INV \s_ledg_o_obuf_RNO[3] (
.I(s_red_err_led),
.O(s_red_err_led_i)
);
// @15:188
FDC s_blue_err_led_Z (
.Q(s_blue_err_led),
.D(s_blue_err_led_0),
.Q(s_ledg_o_c[1]),
.D(s_blue_err_led),
.C(s_clk_c),
.CLR(s_reset_x_i_c)
);
// @15:188
FDC s_green_err_led_Z (
.Q(s_green_err_led),
.D(s_green_err_led_0),
.Q(s_ledg_o_c[2]),
.D(s_green_err_led),
.C(s_clk_c),
.CLR(s_reset_x_i_c)
);
// @15:188
FDC s_red_err_led_Z (
.Q(s_red_err_led),
.D(s_red_err_led_0),
.Q(s_ledg_o_c[3]),
.D(s_red_err_led),
.C(s_clk_c),
.CLR(s_reset_x_i_c)
);
// @15:188
LUT2_L s_blue_err_led_e (
.I0(s_blue_err_led),
.I0(s_ledg_o_c[1]),
.I1(s_blue_err),
.LO(s_blue_err_led_0)
.LO(s_blue_err_led)
);
defparam s_blue_err_led_e.INIT=4'hE;
// @15:188
LUT2_L s_red_err_led_e (
.I0(s_red_err_led),
.I0(s_ledg_o_c[3]),
.I1(s_red_err),
.LO(s_red_err_led_0)
.LO(s_red_err_led)
);
defparam s_red_err_led_e.INIT=4'hE;
// @15:27
OBUF \s_ledg_o_obuf[3] (
.O(s_ledg_o[3]),
.I(s_red_err_led_i)
.I(s_ledg_o_c[3])
);
// @15:27
OBUF \s_ledg_o_obuf[2] (
.O(s_ledg_o[2]),
.I(s_green_err_led_i)
.I(s_ledg_o_c[2])
);
// @15:27
OBUF \s_ledg_o_obuf[1] (
.O(s_ledg_o[1]),
.I(s_blue_err_led_i)
.I(s_ledg_o_c[1])
);
// @15:27
OBUF \s_ledg_o_obuf[0] (
.O(s_ledg_o[0]),
.I(un1_s_ledg_o_i)
.I(un1_s_ledg_o_lut6_2_O6)
);
// @15:26
OBUF s_vsync_o_obuf (
......@@ -8936,18 +8919,20 @@ defparam s_red_err_led_e.INIT=4'hE;
.s_tmr_en(s_tmr_en),
.s_blue_err_1(s_blue_err)
);
LUT3 s_green_err_RNI9N8F_o6 (
.I0(s_blue_err_led),
.I1(s_red_err_led),
.I2(s_green_err_led),
.O(un1_s_ledg_o_i)
);
defparam s_green_err_RNI9N8F_o6.INIT=8'h01;
LUT2 s_green_err_RNI9N8F_o5 (
.I0(s_green_err_led),
// @15:70
LUT3 un1_s_ledg_o_lut6_2_o6 (
.I0(s_ledg_o_c[1]),
.I1(s_ledg_o_c[3]),
.I2(s_ledg_o_c[2]),
.O(un1_s_ledg_o_lut6_2_O6)
);
defparam un1_s_ledg_o_lut6_2_o6.INIT=8'hFE;
// @15:70
LUT2 un1_s_ledg_o_lut6_2_o5 (
.I0(s_ledg_o_c[2]),
.I1(s_green_err),
.O(s_green_err_led_0)
.O(s_green_err_led)
);
defparam s_green_err_RNI9N8F_o5.INIT=4'hE;
defparam un1_s_ledg_o_lut6_2_o5.INIT=4'hE;
endmodule /* spriteflyer_top */
......@@ -21,6 +21,7 @@ impl -add basys3 -type fpga
#
#implementation parameter settings
set_option -hdl_param -set G_CLK_FREQUENCY 100000000
set_option -hdl_param -set G_LED_ON '1'
#device options
set_option -technology Artix7
......@@ -31,7 +32,7 @@ set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "work.spriteflyer_top.rtl"
set_option -top_module "spriteflyer_top"
# mapper_options
set_option -frequency 1.000000
......
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