Skip to content
GitLab
Menu
Projects
Groups
Snippets
/
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
Menu
Open sidebar
vecs
FIJI Public
Commits
389f0fa6
Commit
389f0fa6
authored
Sep 06, 2017
by
Stefan Tauner
Browse files
Document known issues in ISSUES.md
parent
f8f2b5fa
Changes
2
Show whitespace changes
Inline
Side-by-side
ISSUES.md
0 → 100644
View file @
389f0fa6
# Maximum number of FIUs/Test cases
While the code within FIJI does not impose limitations on the number
of Fault Injection Units (FIUs) test cases in configuration files,
the GUI framework used for FIJI Setup and FIJI EE (Tk) as of 2017
contains some bugs that might make it impossible to display a high
number of GUI elements on screen. Some installations have been affected
by this and could not display more than about 300 FIUs.
The only known workaround is to edit the configuration files by hand for
all FIUs greater than this limit.
# No support for multiple instances of the same module
Currently FIJI does only support single instances of modules. However,
no netlist observed so far uses multiple instances of a single module.
Additionally, FIJI prints the driver path only as "module/pathname"
which is inconsistent with the full hierarchical path of the net itself.
What could be done:
*
Print out the full hierarchical path of the driver.
However, this might lead the user to think that FIJI actually supports
multiple instances of a module.
*
Check for duplicate modules when loading a netlist.
*
Check for duplicate modules when validating a driver (by searching for
a duplicate of the respective module at runtime or by comparing it
with a list of duplicate modules created at netlist load time).
*
Add support for duplicate modules.
This would require to instrument the copy of a module.
# Verilog vs. VHDL
While FIJI expects Verilog netlists as input, many files generated by
it such as the top wrapper, FIC and FIUs are coded in VHDL only. Thus
any tools that have to process the instrumented netlist and these
generated files together (e.g., for synthesis) have to support both,
Verilog and VHDL.
README.md
View file @
389f0fa6
...
...
@@ -45,6 +45,8 @@ The following documents are available:
-
API documentation about the source code of FIJI can be built with Doxygen by executing
`make -C ./docs/ doxygen`
.
It requires
`doxygen-filter-perl`
to be available (provided by Perl's
`Doxygen::Filter::Perl`
package).
-
Know issues and limitations are documented in the
[
`ISSUES`
](
/ISSUES.md
)
file.
## Installation
Since FIJI requires a relatively sane Verilog netlist as input, using Synopsis Synplify is recommended and thus needs to be installed.
...
...
Write
Preview
Supports
Markdown
0%
Try again
or
attach a new file
.
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment