Change "toplevel" to "top-level" (adjective) or "top level" (noun) where appropriate

bin/FIJI/Netlist.pm

@@ -103,7 +103,7 @@ sub read_file {
 }
 
 ## @method public get_toplevel_port_names ()
-# @brief retrieves the port names of all toplevel modules
+# @brief retrieves the port names of all top-level modules
 #
 # @returns an array of Verilog::Port references
 sub get_toplevel_port_names {
@@ -123,7 +123,7 @@ sub get_toplevel_port_names {
 }
 
 ## @method public get_toplevel_module ()
-# @brief retrieves the port names of all toplevel modules
+# @brief retrieves the top-level module
 #
 # @returns a Verilog::Module reference
 sub get_toplevel_module {
@@ -131,8 +131,8 @@ sub get_toplevel_module {
     my @m      = $self->{'nl'}->top_modules_sorted;
     my $n      = @m;
     return $m[0] if ($n == 1);
-    return "More than one toplevel module present in netlist" if ($n > 1);
-    return "No toplevel module found";
+    return "More than one top-level module present in netlist" if ($n > 1);
+    return "No top-level module found";
 }
 
 ## @method public get_nets ()
@@ -1400,7 +1400,7 @@ sub _extract_netpath_elements {
     my $mod = $self->{'nl'}->find_module($top_name);
 
     if (!(defined $mod && $mod->isa("Verilog::Netlist::Module") && $mod->is_top())) {
-        return "Net path toplevel module $top_name does not exist";
+        return "Net path of top-level module $top_name does not exist";
     }
 
     my $i;

bin/FIJI/VHDL.pm

@@ -275,7 +275,7 @@ sub _vhdl_escape_identifier {
 #
 # \param netlist        the Verilog-Perl netlist
 # \param fiji_settings  the path to the fiji.cfg file
-# \param dut_toplevel   the toplevel module in the vqm netlist
+# \param dut_toplevel   the top-level module in the vqm netlist
 # \param vhdl_filename  the VHDL file to be generated
 #
 # \returns 0 if VHDL file was generated successfully.
@@ -320,7 +320,7 @@ sub generate_wrapper_module {
     my $vqm_toplevel_module = $nl->find_module($dut_toplevel);
 
     # check inputs
-    return "Toplevel module $dut_toplevel not found." if (!defined $vqm_toplevel_module);
+    return "Top-level module $dut_toplevel not found." if (!defined $vqm_toplevel_module);
     return "Module $dut_toplevel is not at the top level." unless ($vqm_toplevel_module->is_top);
 
     # create lists for vhdl declarations and maps

bin/fiji_instrument.pl

@@ -195,7 +195,7 @@ sub main {
     }
 
     #
-    # Retrieve toplevel module
+    # Retrieve top-level module
     #
 
     my $toplevel_module = $nl->get_toplevel_module();
@@ -338,7 +338,7 @@ sub main {
     # Design ID = CRC-CCITT of all input data:
     # - input netlist (file content excluding full-line comments)
     # - input settings file (file content excluding full-line comments)
-    # - toplevel module name
+    # - top-level module name
     # - file prefix
 
     my $ctx = Digest::CRC->new(type => "crcccitt");
@@ -539,7 +539,7 @@ Netlist file to instrument
 
 =item B<-p, --file-prefix PREFIX
 
-Prefix for all generated files. Default: toplevel module name
+Prefix for all generated files. Default: top-level module name
                                 
 =item B<-o, --output-dir PATH>
 

docs/demos/hx8k_demo/rtl/tinyvga.v

@@ -22,7 +22,7 @@
 //  See the LICENSE file for more details.
 // 
 //  Description:
-//   HX8K Demo Toplevel Module
+//   Top-level module of HX8K Demo
 // ------------------------------------------------------------------------------
 
 `default_nettype none

docs/demos/tmr_vga/fiji/basys3_test_1/synp/README

@@ -8,7 +8,7 @@
     Use Vivado:      YES
     Output Format:   VM
     Output Filename: spriteflyer_top.vm
-    Verilog toplevel module: fiji_top
+    Verilog top-level module: fiji_top
 
 4. Add the following files to the project:
 

docs/demos/tmr_vga/fiji/basys3_test_1/vivado/README

@@ -16,7 +16,7 @@
 
    Set xc7a35tcpg236-1 as device
 
-   Set fiji_top as toplevel module
+   Set fiji_top as top-level module
 
 2. Check pin and clock constraints
 

docs/demos/tmr_vga/fiji/zybo_test_1/synp/README

@@ -8,7 +8,7 @@
     Use Vivado:      YES
     Output Format:   VM
     Output Filename: spriteflyer_top.vm
-    Verilog toplevel module: fiji_top
+    Verilog top-level module: fiji_top
 
 4. Add the following files to the project:
 

docs/technical_reference_manual/content/03-software.tex

@@ -161,7 +161,7 @@ To this end it calculates a 16-bit hash value based on the CRC-CCITT algorithm c
 \begin{itemize}
     \item the unmodified net list (i.e., the content of the Verilog netlist file)
     \item the \ac{FIJI} Settings (i.e., the file contents)
-    \item the (user-settable) name of the toplevel module (wrapper)
+    \item the (user-settable) name of the top-level module (wrapper)
     \item the (user-settable) file prefix
 \end{itemize}
 

docs/technical_reference_manual/content/04-hardware.tex

@@ -111,13 +111,13 @@ registers.
 
 
 \begin{table}
-    \caption{Toplevel VHDL Inputs}
+    \caption{Top-level VHDL Inputs}
     \input{content/tab_vhdl_inputs.tex}
     \label{tab:toplevel_inputs}
 \end{table}
 
 \begin{table}
-    \caption{Toplevel VHDL Outputs}
+    \caption{Top-level VHDL Outputs}
     \input{content/tab_vhdl_outputs.tex}
     \label{tab:toplevel_outputs}
 \end{table}
\ No newline at end of file

docs/user_guide/content/04-setup.tex

@@ -203,14 +203,14 @@ hierarchical path. A hierarchical path shall be constructed as follows in Extend
 \begin{verbatim}
 hierarchical-path = top, "/", { cell-list }, net;
 cell-list         = { cell-list }, cell, "/";
-top               = ? Toplevel module name ?;
+top               = ? Top-level module name ?;
 net               = ? Net name ?;
 cell              = ? Cell name ?;
 \end{verbatim}
 \smallskip
 \end{minipage}
 
-A hierarchical path starts with the name of the toplevel module, then
+A hierarchical path starts with the name of the top-level module, then
 contains a path of instantiation names, and finally, the name of a net.
 The forward slash character \texttt{`/'} is used as a separator between
 module, instantiation, and net names. As extended identifiers may be

docs/user_guide/content/05-instrumentation.tex

@@ -8,7 +8,7 @@ tool.
 Its main task is to actually perform the modifications of the \ac{DUT} netlist
 specified in the \ac{FIJI} configuration file. For each \texttt{[\acs{FIU}$n$]} entry
 in this file, it breaks up the corresponding net into an \textit{original}
-and a \textit{modified} net, routes these nets to the existing toplevel entity, and creates
+and a \textit{modified} net, routes these nets to the existing top-level entity, and creates
 an output and input for them, respectively.
 The resulting modified netlist is saved into a new file as Verilog netlist.
 
@@ -40,7 +40,7 @@ the following parameters and switches:
 
         Changes the filename prefix for all generated files. 
         This parameter is \emph{optional}.
-        If it is not specified, the module name of the toplevel in the \ac{DUT} netlist is used.
+        If it is not specified, the module name of the top level in the \ac{DUT} netlist is used.
 
     \item \texttt{-o, {-}{-}output-dir=<path>}
 

docs/user_guide/content/06-synthesis.tex

@@ -68,7 +68,7 @@ To do this via the Synplify GUI, the following steps have to be executed:
 To do this using a \textit{synthesis} constraints file (\texttt{fdc}), add
 the following constraint:
 \begin{verbatim}
-define_compile_point  {v:[<library>].<DUT toplevel entity name>} -type {locked}
+define_compile_point  {v:[<library>].<DUT top-level entity name>} -type {locked}
 \end{verbatim}
 
 The \textit{library} string point to the library where the \ac{DUT} can be

docs/user_guide/content/07-runtime.tex

@@ -477,7 +477,7 @@ the following steps need to be performed:
         \begin{itemize}
             \item \texttt{<path/to/fiji>/hw/rtl/fault\_selection\_type\_pkg.vhd}:
 
-                  the 'fault selection type' required by the fault injection logic's toplevel
+                  the 'fault selection type' required by the fault injection logic's top level
 
             \item the VHDL configuration package generated by \textit{\ac{FIJI} instrument}
         

docs/user_guide/content/08-demo_tmr.tex

@@ -289,7 +289,7 @@ Replace `basys3` with your board name where applicable.
             \item Zybo: \texttt{xc7z010clg400-1}
         \end{itemize}
 
-    \item Set \texttt{fiji\_top} as toplevel module.
+    \item Set \texttt{fiji\_top} as top-level module.
 
     \item Execute ``Generate Bitstream'' (in the ``Flow Navigator'' on the left on the bottom).
 

hw/tb/fault_injection_top_tb.vhd

@@ -22,7 +22,7 @@
 -- See the LICENSE file for more details.
 --
 -- Description:
---  Fault injection toplevel testbench file
+--  Fault injection top-level testbench file
 --------------------------------------------------------------------------------
 
 library ieee;