Commit 375ac2bb authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

added testcases

parent edb8dac1
; FIJI::ConfigSorted 0.1
; Tue Mar 15 17:44:08 2016
[CONSTS]
BAUDRATE=115200
CFGS_PER_MSG=2
CLOCK_NET=top|clk
FAULT_DETECT_1_EN=0
FAULT_DETECT_1_INVERT=0
FAULT_DETECT_1_NAME=
FAULT_DETECT_2_EN=0
FAULT_DETECT_2_INVERT=0
FAULT_DETECT_2_NAME=
FIU_CFG_BITS=3
FIU_NUM=1
FREQUENCY=50000000
IMPLEMENTATION_TOOL=ALTERA_QUARTUS
INSTRUMENTATION_LOG=fiji_instrument.log
LFSR_POLY=0x2d
LFSR_SEED=0xcafe
LFSR_WIDTH=16
OPTIMIZATIONS=ALLOW
OUTPUT_DIR=.
RESET_DUT_IN_ACTIVE=1
RESET_DUT_IN_DURATION=1
RESET_DUT_IN_EN=0
RESET_DUT_OUT_ACTIVE=1
RESET_DUT_OUT_EN=0
RESET_DUT_OUT_NAME=
RESET_EXT_ACTIVE=1
RESET_EXT_EN=0
RESET_EXT_IN_NAME=s_fiji_reset_i
RX_IN_NAME=s_fiji_rx_i
SYNTHESIS_TOOL=SYNPLIFY_PRO
TIMER_WIDTH=4
TRIGGER_DUT_ACTIVE=1
TRIGGER_DUT_EN=0
TRIGGER_DUT_NAME=
TRIGGER_EXT_ACTIVE=1
TRIGGER_EXT_EN=0
TRIGGER_EXT_IN_NAME=s_fiji_trigger_ext_i
TX_OUT_NAME=s_fiji_tx_o
[FIU0]
DRIVER_PATH=top|~\\****w****
DRIVER_TYPE=ASSIGN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x7
NET_NAME=top|\\++++n++++
; FIJI::ConfigSorted 0.1
; Tue Mar 15 17:44:57 2016
[CONSTS]
BAUDRATE=115200
CFGS_PER_MSG=2
CLOCK_NET=top|clk
FAULT_DETECT_1_EN=0
FAULT_DETECT_1_INVERT=0
FAULT_DETECT_1_NAME=
FAULT_DETECT_2_EN=0
FAULT_DETECT_2_INVERT=0
FAULT_DETECT_2_NAME=
FIU_CFG_BITS=3
FIU_NUM=1
FREQUENCY=50000000
IMPLEMENTATION_TOOL=ALTERA_QUARTUS
INSTRUMENTATION_LOG=fiji_instrument.log
LFSR_POLY=0x2d
LFSR_SEED=0xcafe
LFSR_WIDTH=16
OPTIMIZATIONS=ALLOW
OUTPUT_DIR=.
RESET_DUT_IN_ACTIVE=1
RESET_DUT_IN_DURATION=1
RESET_DUT_IN_EN=0
RESET_DUT_OUT_ACTIVE=1
RESET_DUT_OUT_EN=0
RESET_DUT_OUT_NAME=
RESET_EXT_ACTIVE=1
RESET_EXT_EN=0
RESET_EXT_IN_NAME=s_fiji_reset_i
RX_IN_NAME=s_fiji_rx_i
SYNTHESIS_TOOL=SYNPLIFY_PRO
TIMER_WIDTH=4
TRIGGER_DUT_ACTIVE=1
TRIGGER_DUT_EN=0
TRIGGER_DUT_NAME=
TRIGGER_EXT_ACTIVE=1
TRIGGER_EXT_EN=0
TRIGGER_EXT_IN_NAME=s_fiji_trigger_ext_i
TX_OUT_NAME=s_fiji_tx_o
[FIU0]
DRIVER_PATH=top|~w
DRIVER_TYPE=ASSIGN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x0
NET_NAME=top|n
// testcase 2
// Inject into \++++n++++ ;
// DRIVER: ASSIGN, single-bit net
// DRIVEN: ASSIGN, single-bit net
module top (
i, o, clk
);
input clk;
input i;
output o;
wire \****w**** ;
wire \++++n++++ ;
assign \++++n++++ = ~\****w**** ;
assign o = \++++n++++ ;
cascade cell1 (.in(i), .out(\****w**** ));
endmodule
\ No newline at end of file
// testcase 2
// Inject into n
// DRIVER: ASSIGN, single-bit net
// DRIVEN: ASSIGN, single-bit net
module top (
i, o, clk
);
input clk;
input i;
output o;
wire w;
wire n;
assign n = ~ w;
assign o = n;
cascade cell1 (.in(i), .out(w));
endmodule
\ No newline at end of file
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