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vecs
FIJI Public
Commits
368b547d
Commit
368b547d
authored
Sep 07, 2017
by
Christian Fibich
Committed by
Stefan Tauner
May 04, 2018
Browse files
VGA TMR Demo: Zybo
Added trigger to UM. Added constraint files for Vivado. Added FIU names to cfg
parent
73957fdd
Changes
4
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docs/demos/tmr_vga/fiji/zybo_test_1/fiji/fiji.cfg
View file @
368b547d
; FIJI::ConfigSorted 0.1
; Thu
Apr 13
1
6
:2
7:51
2017
; Thu
Sep 7
1
7
:2
0:35
2017
[CONSTS]
BAUDRATE=115200
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@@ -24,6 +24,7 @@ OUTPUT_DIR=.
RST_DUT_IN_ACT=1
RST_DUT_IN_DUR=1
RST_DUT_IN_EN=0
RST_DUT_IN_NAME=
RST_DUT_OUT_ACT=1
RST_DUT_OUT_EN=1
RST_DUT_OUT_NAME="spriteflyer_top/s_reset_x_i_c"
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@@ -46,6 +47,7 @@ DRIVER_PATH="spriteflyer_sprite_2_1/\\s_sprite_line_Z[0] /Q"
DRIVER_TYPE=PIN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x1
NAME=Sprite Line
NET_NAME="spriteflyer_top/\\generate_tmr_partitions.0.i_sprite /s_sprite_line[0]"
[FIU1]
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@@ -53,6 +55,7 @@ DRIVER_PATH="spriteflyer_sprite_2_1/s_x_state_Z/Q"
DRIVER_TYPE=PIN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x2
NAME=X State
NET_NAME="spriteflyer_top/\\generate_tmr_partitions.0.i_sprite /s_x_state"
[FIU2]
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@@ -60,6 +63,7 @@ DRIVER_PATH="spriteflyer_voter_6/s_green_tmr_partitions"
DRIVER_TYPE=PORT
FAULT_MODEL=RUNTIME
LFSR_MASK=0x3
NAME=VGA Green
NET_NAME="spriteflyer_top/i_voter_green/s_green_tmr_partitions[5]"
docs/demos/tmr_vga/fiji/zybo_test_1/vivado/clock.xdc
0 → 100644
View file @
368b547d
create_clock -period 8.000 -name s_clk_i -waveform {0.000 4.000} [get_ports -filter { NAME =~ "*clk*" && DIRECTION == "IN" }]
docs/demos/tmr_vga/fiji/zybo_test_1/vivado/fiji_pins.xdc
0 → 100644
View file @
368b547d
set_property IOSTANDARD LVCMOS33 [get_ports s_fiji_rx_i]
set_property IOSTANDARD LVCMOS33 [get_ports s_fiji_tx_o]
set_property SLEW FAST [get_ports s_fiji_tx_o]
set_property PACKAGE_PIN V12 [get_ports s_fiji_rx_i]
set_property PACKAGE_PIN W16 [get_ports s_fiji_tx_o]
set_property PACKAGE_PIN P16 [get_ports s_fiji_trig_ext_i]
set_property IOSTANDARD LVCMOS33 [get_ports s_fiji_trig_ext_i]
docs/user_guide/content/08-demo.tex
View file @
368b547d
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@@ -76,7 +76,7 @@ In a real-world design the states of the redundant units would usually be determ
The design generates a 640x480 @ 25Mhz VGA signal.
\item
The dip-switch SW0 controls if TMR is enabled.
\item
BTN0 resets the design when pressed.
% FIXME: E
xternal
T
rigger
\item
The e
xternal
t
rigger
is activated when BTN1 is pressed.
\item
The LEDs above the dip switches (LD0-LD3) show the error detection state:
\begin{itemize}
\item
LD0 shows if any error has been detected.
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