Commit 33b9356d authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

Bus2single testcase added

parent 6114ed02
; FIJI::ConfigSorted 0.1
; Tue Jun 14 11:06:44 2016
[CONSTS]
BAUDRATE=115200
CFGS_PER_MSG=2
CLOCK_NET="top/clk"
FAULT_DETECT_1_EN=0
FAULT_DETECT_1_INVERT=0
FAULT_DETECT_1_NAME=""
FAULT_DETECT_2_EN=0
FAULT_DETECT_2_INVERT=0
FAULT_DETECT_2_NAME=""
FIU_CFG_BITS=3
FIU_NUM=3
FREQUENCY=50000000
IMPLEMENTATION_TOOL=ALTERA_QUARTUS
INSTRUMENTATION_LOG=fiji_instrument.log
LFSR_POLY=0x2d
LFSR_SEED=0xcafe
LFSR_WIDTH=16
OPTIMIZATIONS=ALLOW
OUTPUT_DIR=.
RESET_DUT_IN_ACTIVE=1
RESET_DUT_IN_DURATION=1
RESET_DUT_IN_EN=0
RESET_DUT_OUT_ACTIVE=1
RESET_DUT_OUT_EN=0
RESET_DUT_OUT_NAME=""
RESET_EXT_ACTIVE=1
RESET_EXT_EN=0
RESET_EXT_IN_NAME=s_fiji_reset_i
RX_IN_NAME=s_fiji_rx_i
SYNTHESIS_TOOL=SYNPLIFY_PRO
TIMER_WIDTH=4
TRIGGER_DUT_ACTIVE=1
TRIGGER_DUT_EN=0
TRIGGER_DUT_NAME=""
TRIGGER_EXT_ACTIVE=1
TRIGGER_EXT_EN=0
TRIGGER_EXT_IN_NAME=s_fiji_trigger_ext_i
TX_OUT_NAME=s_fiji_tx_o
[FIU0]
DRIVER_PATH="top/cell1/y_8"
DRIVER_TYPE=PIN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x0
NET_NAME="top/w[8]"
[FIU1]
DRIVER_PATH="top/cell1/y_9"
DRIVER_TYPE=PIN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x0
NET_NAME="top/w[9]"
[FIU2]
DRIVER_PATH="top/cell1/y_c"
DRIVER_TYPE=PIN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x0
NET_NAME="top/w[12]"
// testcase_PIN_PIN_bus_two_nets
// testcase 11
// Inject into w[8], w[9], and w[12]
// DRIVER: PIN, bussed net
// DRIVEN: PIN, bussed net
`undef celldef
`ifdef celldef
module cyclonev_and16 (
IN1,Y
);
input [15:0] IN1;
output [15:0] Y;
assign Y = IN1;
endmodule
`endif
module bus2single ( IN1, y_0, y_1, y_2, y_3, y_4, y_5, y_6, y_7, y_8, y_9, y_a, y_b, y_c, y_d, y_e, y_f);
input [15:0] IN1;
output y_0;
output y_1;
output y_2;
output y_3;
output y_4;
output y_5;
output y_6;
output y_7;
output y_8;
output y_9;
output y_a;
output y_b;
output y_c;
output y_d;
output y_e;
output y_f;
cyclonev_and16 foo(.IN1(IN1),.Y({y_0, y_1, y_2, y_3, y_4, y_5, y_6, y_7, y_8, y_9, y_a, y_b, y_c, y_d, y_e, y_f}));
endmodule
module single2bus (in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8, in_9, in_a, in_b, in_c, in_d, in_e, in_f, Y);
output [15:0] Y;
input in_0;
input in_1;
input in_2;
input in_3;
input in_4;
input in_5;
input in_6;
input in_7;
input in_8;
input in_9;
input in_a;
input in_b;
input in_c;
input in_d;
input in_e;
input in_f;
cyclonev_and16 bar(.IN1({in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8, in_9, in_a, in_b, in_c, in_d, in_e, in_f}),.Y(Y));
endmodule
module top (
i, o, clk
);
input clk;
input [15:0] i;
output [15:0] o;
wire [15:0] w;
bus2single cell1 (.IN1(i),
.y_0(w[0]),
.y_1(w[1]),
.y_2(w[2]),
.y_3(w[3]),
.y_4(w[4]),
.y_5(w[5]),
.y_6(w[6]),
.y_7(w[7]),
.y_8(w[8]),
.y_9(w[9]),
.y_a(w[10]),
.y_b(w[11]),
.y_c(w[12]),
.y_d(w[13]),
.y_e(w[14]),
.y_f(w[15])
);
single2bus cell2 (.Y(o),
.in_0(w[0]),
.in_1(w[1]),
.in_2(w[2]),
.in_3(w[3]),
.in_4(w[4]),
.in_5(w[5]),
.in_6(w[6]),
.in_7(w[7]),
.in_8(w[8]),
.in_9(w[9]),
.in_a(w[10]),
.in_b(w[11]),
.in_c(w[12]),
.in_d(w[13]),
.in_e(w[14]),
.in_f(w[15])
);
endmodule
\ No newline at end of file
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