Commit 32de0019 authored by Stefan Tauner's avatar Stefan Tauner
Browse files

instrument unit tests: add further tests focused on concatenations

parent 3938cce1
; FIJI::ConfigSorted 0.1
; Fri Apr 1 19:28:56 2016
[CONSTS]
BAUDRATE=115200
CFGS_PER_MSG=2
CLOCK_NET=top/clk
FAULT_DETECT_1_EN=0
FAULT_DETECT_1_INVERT=0
FAULT_DETECT_1_NAME=
FAULT_DETECT_2_EN=0
FAULT_DETECT_2_INVERT=0
FAULT_DETECT_2_NAME=
FIU_CFG_BITS=3
FIU_NUM=1
FREQUENCY=50000000
IMPLEMENTATION_TOOL=ALTERA_QUARTUS
INSTRUMENTATION_LOG=fiji_instrument.log
LFSR_POLY=0x2d
LFSR_SEED=0xcafe
LFSR_WIDTH=16
OPTIMIZATIONS=ALLOW
OUTPUT_DIR=.
RESET_DUT_IN_ACTIVE=1
RESET_DUT_IN_DURATION=1
RESET_DUT_IN_EN=0
RESET_DUT_OUT_ACTIVE=1
RESET_DUT_OUT_EN=0
RESET_DUT_OUT_NAME=
RESET_EXT_ACTIVE=1
RESET_EXT_EN=0
RESET_EXT_IN_NAME=s_fiji_reset_i
RX_IN_NAME=s_fiji_rx_i
SYNTHESIS_TOOL=SYNPLIFY_PRO
TIMER_WIDTH=4
TRIGGER_DUT_ACTIVE=1
TRIGGER_DUT_EN=0
TRIGGER_DUT_NAME=
TRIGGER_EXT_ACTIVE=1
TRIGGER_EXT_EN=0
TRIGGER_EXT_IN_NAME=s_fiji_trigger_ext_i
TX_OUT_NAME=s_fiji_tx_o
[FIU0]
DRIVER_PATH=top/w
DRIVER_TYPE=ASSIGN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x0
NET_NAME=top/n[0]
; FIJI::ConfigSorted 0.1
; Fri Apr 1 19:37:06 2016
[CONSTS]
BAUDRATE=115200
CFGS_PER_MSG=2
CLOCK_NET=top/clk
FAULT_DETECT_1_EN=0
FAULT_DETECT_1_INVERT=0
FAULT_DETECT_1_NAME=
FAULT_DETECT_2_EN=0
FAULT_DETECT_2_INVERT=0
FAULT_DETECT_2_NAME=
FIU_CFG_BITS=3
FIU_NUM=1
FREQUENCY=50000000
IMPLEMENTATION_TOOL=ALTERA_QUARTUS
INSTRUMENTATION_LOG=fiji_instrument.log
LFSR_POLY=0x2d
LFSR_SEED=0xcafe
LFSR_WIDTH=16
OPTIMIZATIONS=ALLOW
OUTPUT_DIR=.
RESET_DUT_IN_ACTIVE=1
RESET_DUT_IN_DURATION=1
RESET_DUT_IN_EN=0
RESET_DUT_OUT_ACTIVE=1
RESET_DUT_OUT_EN=0
RESET_DUT_OUT_NAME=
RESET_EXT_ACTIVE=1
RESET_EXT_EN=0
RESET_EXT_IN_NAME=s_fiji_reset_i
RX_IN_NAME=s_fiji_rx_i
SYNTHESIS_TOOL=SYNPLIFY_PRO
TIMER_WIDTH=4
TRIGGER_DUT_ACTIVE=1
TRIGGER_DUT_EN=0
TRIGGER_DUT_NAME=
TRIGGER_EXT_ACTIVE=1
TRIGGER_EXT_EN=0
TRIGGER_EXT_IN_NAME=s_fiji_trigger_ext_i
TX_OUT_NAME=s_fiji_tx_o
[FIU0]
DRIVER_PATH=top/{w[15:0]}
DRIVER_TYPE=ASSIGN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x0
NET_NAME=top/n[0]
; FIJI::ConfigSorted 0.1
; Mon Apr 4 02:17:12 2016
[CONSTS]
BAUDRATE=115200
CFGS_PER_MSG=2
CLOCK_NET="top/clk"
FAULT_DETECT_1_EN=0
FAULT_DETECT_1_INVERT=0
FAULT_DETECT_1_NAME=""
FAULT_DETECT_2_EN=0
FAULT_DETECT_2_INVERT=0
FAULT_DETECT_2_NAME=""
FIU_CFG_BITS=3
FIU_NUM=1
FREQUENCY=50000000
IMPLEMENTATION_TOOL=ALTERA_QUARTUS
INSTRUMENTATION_LOG=fiji_instrument.log
LFSR_POLY=0x2d
LFSR_SEED=0xcafe
LFSR_WIDTH=16
OPTIMIZATIONS=ALLOW
OUTPUT_DIR=.
RESET_DUT_IN_ACTIVE=1
RESET_DUT_IN_DURATION=1
RESET_DUT_IN_EN=0
RESET_DUT_OUT_ACTIVE=1
RESET_DUT_OUT_EN=0
RESET_DUT_OUT_NAME=""
RESET_EXT_ACTIVE=1
RESET_EXT_EN=0
RESET_EXT_IN_NAME=s_fiji_reset_i
RX_IN_NAME=s_fiji_rx_i
SYNTHESIS_TOOL=SYNPLIFY_PRO
TIMER_WIDTH=4
TRIGGER_DUT_ACTIVE=1
TRIGGER_DUT_EN=0
TRIGGER_DUT_NAME=""
TRIGGER_EXT_ACTIVE=1
TRIGGER_EXT_EN=0
TRIGGER_EXT_IN_NAME=s_fiji_trigger_ext_i
TX_OUT_NAME=s_fiji_tx_o
[FIU0]
DRIVER_PATH="top/{w[1],w[0],w[15:2]}"
DRIVER_TYPE=ASSIGN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x0
NET_NAME="top/n[0]"
; FIJI::ConfigSorted 0.1
; Tue Apr 5 03:27:53 2016
[CONSTS]
BAUDRATE=115200
CFGS_PER_MSG=2
CLOCK_NET="top/clk"
FAULT_DETECT_1_EN=0
FAULT_DETECT_1_INVERT=0
FAULT_DETECT_1_NAME=""
FAULT_DETECT_2_EN=0
FAULT_DETECT_2_INVERT=0
FAULT_DETECT_2_NAME=""
FIU_CFG_BITS=3
FIU_NUM=1
FREQUENCY=50000000
IMPLEMENTATION_TOOL=ALTERA_QUARTUS
INSTRUMENTATION_LOG=fiji_instrument.log
LFSR_POLY=0x2d
LFSR_SEED=0xcafe
LFSR_WIDTH=16
OPTIMIZATIONS=ALLOW
OUTPUT_DIR=.
RESET_DUT_IN_ACTIVE=1
RESET_DUT_IN_DURATION=1
RESET_DUT_IN_EN=0
RESET_DUT_OUT_ACTIVE=1
RESET_DUT_OUT_EN=0
RESET_DUT_OUT_NAME=""
RESET_EXT_ACTIVE=1
RESET_EXT_EN=0
RESET_EXT_IN_NAME=s_fiji_reset_i
RX_IN_NAME=s_fiji_rx_i
SYNTHESIS_TOOL=SYNPLIFY_PRO
TIMER_WIDTH=4
TRIGGER_DUT_ACTIVE=1
TRIGGER_DUT_EN=0
TRIGGER_DUT_NAME=""
TRIGGER_EXT_ACTIVE=1
TRIGGER_EXT_EN=0
TRIGGER_EXT_IN_NAME=s_fiji_trigger_ext_i
TX_OUT_NAME=s_fiji_tx_o
[FIU0]
DRIVER_PATH="top/{w[1],w[0],w[15:2]}"
DRIVER_TYPE=ASSIGN
FAULT_MODEL=RUNTIME
LFSR_MASK=0x0
NET_NAME="top/n[7]"
// Inject into n[0]
// DRIVER: ASSIGN, bussed net
// DRIVEN: ASSIGN, bussed net, via concatenation
`undef celldef
`ifdef celldef
module cyclonev_and16 (
IN1,Y
);
input [15:0] IN1;
output [15:0] Y;
assign Y = IN1;
endmodule
`endif
module top (
i, o, clk
);
input clk;
input [15:0] i;
output [15:0] o;
wire [15:0] w;
wire [15:0] n;
assign n = w;
assign o = {n[15:0]};
cyclonev_and16 cell1 (.IN1(i), .Y(w));
endmodule
\ No newline at end of file
// Inject into n[0]
// DRIVER: ASSIGN, bussed net, via concatenation
// DRIVEN: ASSIGN, bussed net
`undef celldef
`ifdef celldef
module cyclonev_and16 (
IN1,Y
);
input [15:0] IN1;
output [15:0] Y;
assign Y = IN1;
endmodule
`endif
module top (
i, o, clk
);
input clk;
input [15:0] i;
output [15:0] o;
wire [15:0] w;
wire [15:0] n;
assign n = {w[15:0]};
assign o = n;
cyclonev_and16 cell1 (.IN1(i), .Y(w));
endmodule
\ No newline at end of file
// Inject into n[0]
// DRIVER: ASSIGN, bussed net, individually via concatenation
// DRIVEN: ASSIGN, bussed net
`undef celldef
`ifdef celldef
module cyclonev_and16 (
IN1,Y
);
input [15:0] IN1;
output [15:0] Y;
assign Y = IN1;
endmodule
`endif
module top (
i, o, clk
);
input clk;
input [15:0] i;
output [15:0] o;
wire [15:0] w;
wire [15:0] n;
assign n = {w[1],w[0],w[15:2]};
assign o = n;
cyclonev_and16 cell1 (.IN1(i), .Y(w));
endmodule
\ No newline at end of file
// Inject into n[7]
// DRIVER: ASSIGN, bussed net, individually from a range via concatenation
// DRIVEN: ASSIGN, bussed net
`undef celldef
`ifdef celldef
module cyclonev_and16 (
IN1,Y
);
input [15:0] IN1;
output [15:0] Y;
assign Y = IN1;
endmodule
`endif
module top (
i, o, clk
);
input clk;
input [15:0] i;
output [15:0] o;
wire [15:0] w;
wire [15:0] n;
assign n = {w[1],w[0],w[15:2]};
assign o = n;
cyclonev_and16 cell1 (.IN1(i), .Y(w));
endmodule
\ No newline at end of file
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