Commit 31d4d679 authored by Stefan Tauner's avatar Stefan Tauner
Browse files

netlist: refine error messages for re-instrumented vectors

parent 6f73ba18
......@@ -643,8 +643,9 @@ sub instrument_net {
return "Could not find net or port in module \"" . $mod->name . "\" matching LHS of assignment \"" . $connection->lhs . "\" = \"" . $connection->rhs . "\"";
}
# FIXME: so this is actually a port...
$logger->fatal("Found port name in continuous assignment. This is not supported yet.");
return "BORKED";
my $msg = "Found port name in continuous assignment. This is not supported yet.";
$logger->fatal($msg);
return $msg;
}
$driver = $connection;
if (defined($connection->userdata->{'fiji_driver_bit'})) {
......@@ -694,7 +695,7 @@ sub instrument_net {
$net_tmp->lsb($net->lsb);
$net_tmp->data_type("[".$net->msb.":".$net->lsb."]");
# Additionally the previous exporting of the original signal needs to be adepted
# Additionally the previous exporting of the original signal needs to be adapted
foreach my $statement ($mod->statements) {
if ($statement->rhs =~ /^[ \t]*~?[ \t]*\Q$net_name_tmp\E$/) {
$statement->rhs($net_name_tmp."[".$prev_bit."]");
......@@ -713,8 +714,9 @@ sub instrument_net {
}
}
} elsif (ref($prev_driver) eq "Verilog::Netlist::Port") {
$logger->debug(" reassigning port \"" . $prev_driver->name . "\"");
return "BORKED"; # not implemented yet
my $msg = "Allegedly we have instrumented another bit of port \"" . $prev_driver->name . "\" previously without creating a temporary vector. If true, this would be a bug.";
$logger->fatal($msg);
return $msg;
} elsif (ref($prev_driver) eq "Verilog::Netlist::ContAssign") {
$logger->debug(" reassigning ContAssign \"" . $prev_driver->lhs . " = " . $prev_driver->rhs . "\"");
$prev_driver->rhs($net_name_tmp."[".$prev_bit."]");
......
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