Tex: add RTL abbreviation

docs/tex_common/abbreviations.tex

@@ -8,6 +8,7 @@
 \acro{LHS}{Left-Hand Side}\glsunset{LHS}
 \acro{LOC}{Lines Of Code}
 \acro{LUT}{Look-up Table}
+\acro{RTL}{Register-transfer Level}\glsunset{RTL}
 \acro{SEU}{Single Event Upset}
 \acro{TMR}{Triple Modular Redundancy}\glsunset{TMR}
 \acro{TRM}{Technical Reference Manual}

docs/user_guide/content/01-intro.tex

@@ -5,7 +5,7 @@ Some technical details that are supposedly irrelevant to ordinary users are omit
 
 The \ac{FIJI} suite provides a tool flow for
 performing fault injection tests on chip designs in an FPGA-based environment.
-In contrast to fault injection tests by modification of the RTL source,
+In contrast to fault injection tests by modification of the \ac{RTL} source,
 \ac{FIJI} targets the already synthesized design at the FPGA primitive level (e.g.,
 \acp{LUT}, Flip-Flops, and the nets connecting them). Compared to fault injection
 carried out with the help of partial reconfiguration, \ac{FIJI} is relatively

docs/user_guide/content/07-runtime.tex

@@ -260,7 +260,7 @@ following \emph{optional} command-line arguments:
 The main elements of the \textit{\ac{FIJIEE} GUI} can be seen in \Cref{fig:download_gui}:
 \begin{enumerate}[(1)]
     \item The \textit{Control Area} is used for loading and saving \textit{\ac{FIJI} Tests} files, as well as
-          for exporting test runs to \textit{\ac{FIJI} Tests} files or templates for RTL and gate-level simulation.
+          for exporting test runs to \textit{\ac{FIJI} Tests} files or templates for \ac{RTL} and gate-level simulation.
           Here the user can also select the UART device to be used for communication with the \ac{FIJI} logic.
     \item The \textit{Tab Area} switches between test modes.
     \item In the \textit{Main Area}, the tests in the selected mode
@@ -433,9 +433,9 @@ following entries:
           the completed test run as a \textit{\ac{FIJI} Tests} file for 
           later re-execution.
     \item \textit{As RTL Simulation Template}: This will export the current
-          test run to VHDL-2008 and System Verilog templates for RTL simulation.
+          test run to VHDL-2008 and System Verilog templates for \ac{RTL} simulation.
           This HDL description contains (1) fault injection logic templates
-          which have to be integrated into the various RTL modules manually,
+          which have to be integrated into the various \ac{RTL} modules manually,
           and (2) a scheduling process which controls these templates using
           hierarchical identifiers whose path also has to be adapted.
     \item \textit{As VHDL architecture for gate-level simulation}: This

docs/user_guide/content/09-demo_yosys.tex

@@ -63,7 +63,7 @@ executed in that order):
         \begin{lstlisting}[style=shell,gobble=12]
             $ make fiji-instrument
         \end{lstlisting}
-          to synthesize the RTL design to a Verilog netlist, call FIJI Setup,
+          to synthesize the \ac{RTL} design to a Verilog netlist, call FIJI Setup,
           and finally instrument the netlist as required. A FIJI configuration
           for some faults has already been provided. If necessary, select the
           correct nets/drivers (other Yosys versions might generate a differing