The use case is designated for use with the Cyclone III-based DE0 development
board from Terasic\footnote{\url{http://de0.terasic.com.tw/}, visited on August 29,2016}
or the Zynq-based Zybo\footnote{\url{https://www.xilinx.com/products/boards-and-kits/1-4azfte.html}, visited on August 29, 2016}
board from Terasic\footnote{\url{http://de0.terasic.com.tw}, visited on August~29, 2016},
the Artix~7-based Basys~3\footnote{\url{https://reference.digilentinc.com/reference/programmable-logic/basys-3/start}, visited on April~12, 2017},
or the Zynq~7000-based Zybo\footnote{\url{https://reference.digilentinc.com/reference/programmable-logic/zybo/start}, visited on April~12, 2017},
but is portable to other boards providing a \ac{VGA} connector with little effort.
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\subsection{Hardware Setup}
Board setup (DE0):
\subsubsection{Digilent Basys 3}
\begin{itemize}
\item Connect a 3V3 Serial TTL cable to the DE0:
\item Connect the host with the micro USB port (PROG).
This will not only allow programming the FPGA but also transport the UART packets for the run-time communication.
\item Connect a VGA-compatible monitor to the VGA port.
The design generates a 640x480 @ 25Mhz VGA signal.
\item The dip-switch SW0 controls if TMR is enabled (towards the board edge is off).
\item BTNC resets the design when pressed.
\item The four rightmost LEDs above the dip switches (LD0-LD3) show the error detection state:
\begin{itemize}
\item Connect \textit{Ground} to any GND pin on GPIO1 (e.g., J5.30)
\item Connect \textit{TXD (Host-to-Device)} to GPIO1\_D31 (J5.40)
\item Connect \textit{RXD (Device-to-Host)} to GPIO1\_D30 (J5.39)
\item Leave \textit{\#RTS} unconnected
\item Connect \textit{\#CTS} to GND (or leave unconnected if your cable
pulls it down)
\item LD0 shows if any error has been detected.
\item LD1-3 show which voter (Red, Green, Blue) detected the error.
\end{itemize}
\end{itemize}
\subsubsection{Digilent Zybo}
\begin{itemize}
\item Connect a 3V3 Serial TTL cable to the Zybo:
\begin{itemize}
\item Connect \textit{Ground} to PMOD JE5.
\item Connect \textit{TXD (Host-to-Device)} to PMOD JE1.
\item Connect \textit{RXD (Device-to-Host)} to PMOD JE2.
\item Leave \textit{\#RTS} unconnected.
\item Connect \textit{\#CTS} to GND (or leave unconnected if your cable pulls it down).
\item If your cable requires an I/O voltage input (e.g., FTDI TTL-232R-VIP),
connect the correspondig wire to any 3V3 pin on GPIO1 (e.g., J5.29)
connect the correspondig wire to PMOD JE6.
\end{itemize}
\item Connect a VGA-compatible monitor to the VGA port. The design
generates a 640x480 \@ 25Mhz VGA signal.
\item Connect a VGA-compatible monitor to the VGA port.
The design generates a 640x480 @ 25Mhz VGA signal.
\item The dip-switch SW0 controls if TMR is enabled.
\item BUTTON0 resets the design
\item The green LEDs above the three buttons (LEDG0-LEDG3) show the
error detection state:
\item BTN0 resets the design when pressed.
\item The LEDs above the dip switches (LD0-LD3) show the error detection state:
\begin{itemize}
\item LEDG0 shows if any error has been detected
\item LEDG1-3 show which voter (Red,Green,Blue) detected the error
\item LD0 shows if any error has been detected.
\item LD1-3 show which voter (Red,Green,Blue) detected the error.
\end{itemize}
\end{itemize}
Board setup (Zybo):
\subsubsection{Terasic DE0}
\begin{itemize}
\item Connect a 3V3 Serial TTL cable to the Zybo:
\item Connect a 3V3 Serial TTL cable to the DE0:
\begin{itemize}
\item Connect \textit{Ground} to PMOD JE5
\item Connect \textit{TXD (Host-to-Device)} to PMOD JE1
\item Connect \textit{RXD (Device-to-Host)} to PMOD JE2
\item Leave \textit{\#RTS} unconnected
\item Connect \textit{\#CTS} to GND (or leave unconnected if your cable
pulls it down)
\item Connect \textit{Ground} to any GND pin on GPIO1 (e.g., J5.30).
\item Connect \textit{TXD (Host-to-Device)} to GPIO1\_D31 (J5.40).
\item Connect \textit{RXD (Device-to-Host)} to GPIO1\_D30 (J5.39).
\item Leave \textit{\#RTS} unconnected.
\item Connect \textit{\#CTS} to GND (or leave unconnected if your cable pulls it down).
\item If your cable requires an I/O voltage input (e.g., FTDI TTL-232R-VIP),
connect the correspondig wire to PMOD JE6
connect the correspondig wire to any 3V3 pin on GPIO1 (e.g., J5.29).
\end{itemize}
\item Connect a VGA-compatible monitor to the VGA port.
\item The dip-switch SW0 controls if TMR is enabled.
\itemBTN0 resets the design when pressed
\itemThe LEDs above the dip switches (LD0-LD3) show the
error detection state:
The design generates a 640x480 @ 25Mhz VGA signal.
\itemThe dip-switch SW0 controls if TMR is enabled (towards the board edge is off).
\itemBUTTON0 resets the design.
\item The green LEDs above the three buttons (LEDG0-LEDG3) show the error detection state:
\begin{itemize}
\item LD0 shows if any error has been detected
\item LD1-3 show which voter (Red,Green,Blue) detected the error
\item LEDG0 shows if any error has been detected.
\item LEDG1-3 show which voter (Red,Green,Blue) detected the error.
\end{itemize}
\end{itemize}
\subsection{Work Flow}
All paths hereinafter are relative to \texttt{<FIJI ROOT>/docs/demos/tmr\_vga}.
Due to the various supported boards there are some important points to consider when following the steps:
\begin{itemize}
\item All paths hereinafter are relative to \texttt{<FIJI ROOT>/docs/demos/tmr\_vga}.
\item Parts of them are also \textbf{board-specific} and targeting the DE0.
They have to be changed for any other board accordingly (\texttt{de0}\textrightarrow{}\texttt{basys3}, \texttt{zybo} etc).
\item Depending on the FPGA vendor there are some important differences.
Most of them are written out explicitly in the P\&R description to distinguish between Altera Quartus and Xilinx Vivado.
Another thing that needs to be changed throughout this tutorial if you are using a Xilinx-based board is the file name suffix of netlists:
Instead of \texttt{.vqm} used by Altera you need to use \texttt{.vm} for Xilinx.
\end{itemize}
To reconstruct the execution of the flow to configure, instrument and synthesize the design with injection logic, the following steps have to be executed.
\subsubsection{Input Netlist}
To reconstruct the execution of the flow to configure, instrument and synthesis the design with injection logic, the following steps have to be executed.
The steps hereinafter assume that you have already synthesized a netlist of the original design with Synopsis Synplify.
A suitable Synopsis project and constraint file is provided in \texttt{synp/de0/}.
Synthesizing this with Synplify creates a netlist compatible to our tool (or more specifically to Verilog-Perl).
The resulting file should be located in the \texttt{synp} directory (e.g., synp/de0/de0/spriteflyer\_top.vqm).
\subsubsection{Run setup}
A pre-configured settings file for \ac{FIJI} is located in \texttt{fiji/de0\_test\_1/fiji/fiji.cfg}.
To review the configuration you can open it up in the \ac{FIJI} Setup GUI: