Commit 29fb896c authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

Added benchmark Verilog code + current status dump

parent bc2462e6
/*
* Benchmark Verilog "Netlist" File
* If Verilog-Perl interconnects this correctly, we're happy...
*
* $LastChangedBy$
* $LastChangedDate$
*/
/*
* This is the Cell definition.
* It would be located in the FPGA primitive library, which we don't want to
* load, thus Verilog::Perl has no knowledge about the port widths
*
* module mod (a,y);
* input [3:0] a;
* output y;
* wire [3:0] b;
* wire c;
*
* // Some Functionality
*
* endmodule
*
*/
module top(i,o);
input [31:0] i;
output [31:0] o;
wire [3:0] somebus, someotherbus;
wire somenet_1,somenet_2;
wire [29:0] somewidebus;
assign somewidebus=i[31:2];
assign o[1]=somenet_1;
assign o[2]=somenet_2;
assign o[0]=1'b0;
assign o[3]=someotherbus[2];
assign o[28:4]=25'b0;
assign o[31]=~somenet_1;
mod instmod_1 (
.a(somebus),
.y(somenet_1)
);
mod instmod_2 (
.a(somebus),
.y(someotherbus[2])
);
mod instmod_3 (
.a(somewidebus[24:21]),
.y(somenet_2)
);
mod instmod_4 (
.a(i[31:27]),
.y(o[29])
);
mod instmod_5 (
.a({somenet_1,someotherbus[2],somewidebus[2:1]}),
.y(o[30])
);
/*
FIXME Not allowed in Verilog Language??
mod instmod_6 (
.a[0](somenet_1),
.a[1](someotherbus[2]),
.a[3:2](somewidebus[2:1])
.y(o[31]);
);
*/
endmodule
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