Commit 1cebc246 authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

Added comments to scripts

Added port to Makefile so we don't have to edit test config files
parent 0d91d80e
......@@ -62,7 +62,8 @@ sub _test_fi_uart {
reset => $reset,
consts => $fiji_consts,
);
# FIXME timeout must correspond to t1_duration/t2_duration
# FIXME timeout must correspond to t1_duration*fclk and t2_duration*fclk and
# trigger settings
return $port->send_config( \%config, 1000, 0, 1 );
}
......@@ -70,7 +71,7 @@ sub _test_fi_uart {
## Download tests contained in the .cfg file
# Params
# portname Optional serial port to use
sub download_auto ($;$$) {
sub download_auto ($) {
my $msg;
my $logger = get_logger();
my ($self,$portname) = @_;
......@@ -92,6 +93,7 @@ sub download_auto ($;$$) {
$logger->info("Downloading in auto mode.");
# download tests until halted
while(1) {
for (my $ti = $toff; $ti < @{$fiji_tests->{'tests'} }; $ti++) {
......@@ -112,6 +114,7 @@ sub download_auto ($;$$) {
}
}
# FIXME Repeat information comes from tests config file. OK?
if($fiji_tests->{'design'}->{'REPEAT'} == 0) {
last;
} else {
......@@ -186,7 +189,7 @@ sub download_manual ($;$) {
my $fiji_tests = $self->{'fiji_tests'};
my $fiji_design_consts = $fiji_tests->{'ext'}->{'global_settings'}->{'design'};
# FIXME UART information can be defined in tests config file. OK?
$portname = $self->{'fiji_tests'}->{'design'}->{'UART'} if (!defined $portname);
my $port =
......@@ -336,6 +339,8 @@ sub _get_test_from_stdin {
# test->{'TIMER_VALUE_1'}
# test->{'TIMER_VALUE_2'}
# test->{"FIU_[0..FIU_NUM]_PATTERN_[0..CFGS_PER_MSG]"}
# test->{'RESET_DUT_AFTER_CONFIG'}
# test->{'TRIGGER'}
# portname Optional serial port to use
sub download_test ($$) {
my $logger = get_logger();
......@@ -345,6 +350,8 @@ sub download_test ($$) {
my $fiji_design_consts = $fiji_tests->{'ext'}->{'global_settings'}->{'design'};
my @payload;
# first generate FIU configuration payload
for (my $i = 0 ; $i < $fiji_design_consts->{'FIU_NUM'} ; $i++)
{
for (my $t = 1 ; $t <= $fiji_design_consts->{'CFGS_PER_MSG'} ; $t++)
......@@ -362,6 +369,8 @@ sub download_test ($$) {
}
}
# then generate fixed configuration part (timers,trigger,reset)
my $t1_duration = $test->{'TIMER_VALUE_1'};
$logger->debug(
sprintf( "t1 duration is %d (0x%x).", $t1_duration, $t1_duration )
......@@ -391,10 +400,14 @@ sub download_test ($$) {
$logger->debug(
sprintf( "reset is %sabled.", $reset == 0 ? "dis" : "en" ) );
# download test via serial
my $recv_msg = _test_fi_uart(
$port, \@payload, $t1_duration,
$t2_duration, $trigger_en, $trigger_ext,
$reset, $fiji_design_consts);
return $recv_msg;
}
## Check the hash returned by _test_fi_uart() against HALT_ON_xxx-conditions
......@@ -409,6 +422,8 @@ sub _check_halt ($) {
my $fiji_tests = $self->{'fiji_tests'};
# FIXME HALT_on_xxx information is defined in tests config file. OK?
if ( $recv_msg->{'msg_type'} eq "UNDERRUN" ) {
$logger->info( "UNDERRUN message received. HALT_ON_UNDERRUN = "
. $fiji_tests->{'design'}->{'HALT_ON_UNDERRUN'}
......
......@@ -275,6 +275,19 @@ sub _add_port_to_hierarchy($$$;$) {
return $np;
}
# Generate external access to a single net
# Performs the following steps:
# 1. check if the default port name does not yet exist
# 1a. if it exists, generate a new net name
# 2. add a port through the entire hierarchy
# 3. assign the net to the port using a contassign statement
#
# params:
# net the Verilog::Net object to be used
# function the function out of FIJI::VHDL->FIJI_PORTTYPE_xxx
# port_name how the port shall be named (will be prefixed with "fiji_")
# index for some FIJI_PORTTYPEs, an index is needed (FIU and Fault Detect)
sub net_add_function ($$$;$) {
my $logger = get_logger();
my ($self,$net,$function,$port_name,$index) = @_;
......@@ -297,8 +310,7 @@ sub net_add_function ($$$;$) {
$logger->debug("Connecting Port ".$op->name." to net ".$net->name);
#$op->net($net); should have a net already
# connect the net to the newly created port
$net->module->new_contassign (keyword => "assign",
lhs => $op->name,
rhs => $net->name,
......@@ -308,11 +320,15 @@ sub net_add_function ($$$;$) {
return undef;
}
# generates external access to a specified net
# instruments a single net for fault injection
# 1. tries to determine the driver, or otherwise prompts the user to select it
# 2. generate external access output and input ports
# 3. interconnects these ports to the matching driver and driven cells
#
# params
# net the net to instrument
# driver the driver of this net (can be pin, port or contassign)
# net the Verilog::Net to instrument
# fiu_idx the FIU number this external access shall be connected to
# driver the driver of this net (can be pin, port or contassign) (optional)
sub instrument_net ($$;$) {
#FIXME only works with single-bit pins/ports/nets
my $logger = get_logger();
......@@ -497,7 +513,6 @@ sub _connection_tostr($) {
# -> connection_hashref->{'driven'} contains a list of driven cells
# -> connection_hashref->{'connected'} contains a list cells connected to the
# net but driver/driven cannot be decided
sub _get_net_connections ($$) {
my $logger = get_logger();
my ($self,$net,$connection_hashref) = @_;
......@@ -653,7 +668,13 @@ sub _export_module($) {
for (my $i = 0; $i < @ports; $i++) {
my $port = $ports[$i];
# add port declaration to module header part "module (<PORTS>)"
$module_header .= " ".$port->name;
# port direction
# Verilog::Perl specifies them as 'in', 'out', or 'inout'
# Correct Verilog syntax is 'input', 'output' or 'inout'
# => Add the suffix 'put' where applicable
my $direction = $port->direction.(($port->direction =~ m/^(in|out)$/) ? "put" : "");
my $comment = "";
......@@ -661,6 +682,8 @@ sub _export_module($) {
$comment = " /* FIJI */";
}
# add port declaration to net declaration part "input <FOO>; output <BAR>; wire <SOME_WIRE>"
# data_type also contains the vector specification ([7:0]) where applicable
$net_declarations .= sprintf(" %-6s %+7s %s;%s\n",$direction,(defined $port->data_type) ? $port->data_type : "",$port->name,$comment);
if($i < @ports - 1) {
$module_header .= ",";
......@@ -674,7 +697,8 @@ sub _export_module($) {
foreach my $net ($mod->nets) {
if($net->net_type ne "" && $net->decl_type eq "net") {
# net type is empty when this net belongs to a bussed port.
# don't declare nets with empty net_type
# FIXME when do we get empty net_types?
$net_declarations .= sprintf(" %-6s %+7s %s;\n",$net->net_type,(defined $net->data_type) ? $net->data_type : "",$net->name);
}
}
......@@ -684,14 +708,15 @@ sub _export_module($) {
$logger->info("Generating assigns for module ".$mod->name);
# need to separate assigns from defparams - see below...
# NOTE we need to separate assigns from defparams because Quartus requires
# the defparams setting LUT mask etc.to be right after the cell instantiation.
foreach my $statement ($mod->statements_sorted) {
if(ref($statement) eq "Verilog::Netlist::ContAssign") {
push @contassigns, $statement;
$assign_indent = length $statement->lhs if (length $statement->lhs > $assign_indent);
} elsif (ref($statement) eq "Verilog::Netlist::Defparam") {
# Build a hash of defparams, with the key being the cell identifier.
# FIXME this regex might break with other synthesis tool because of other delimiters (?)
# FIXME this regex might break with other synthesis tool because of other delimiters
my $k = (split(/\./,$statement->lhs))[0];
push @{$defparams{$k}}, $statement;
}
......@@ -727,6 +752,7 @@ sub _export_module($) {
delete $defparams{$cellname};
}
# all defparams should be matched with a cell
foreach my $k (keys (%defparams)) {
$logger->warn("Defparam ".$defparams{$k}->lhs." could not be matched with a cell");
$instantiations .= sprintf(" defparam %-${defparam_indent}s = %s;\n",$defparams{$k}->lhs,$defparams{$k}->rhs);
......
......@@ -41,6 +41,8 @@ use File::Spec;
# FIXME rather similar to Settings.pm
# Can we generalize this?
# FIXME which data has to be present in a test configuration file?
## @function new ($phase, $fiji_ini_file, $existing_settings)
# Create a new settings instance.
#
......@@ -81,6 +83,9 @@ sub new ($;$$) {
return $fiji_settings_ref; # actually an error message
}
} elsif(defined($fiji_cfg) && defined($num_tests)) {
# create a default instance
$fiji_settings_ref->{'design'} = {};
for my $k (keys(TESTCONSTMAP)) {
$fiji_settings_ref->{'design'}->{$k} = TESTCONSTMAP->{$k}->{'default'};
......@@ -103,7 +108,7 @@ sub new ($;$$) {
}
} else {
my $msg = "I need a FIJI::Config one way or another";
my $msg = "FIJI::Config is required (either in Tests-settings file or as a parameter).";
$logger->error($msg);
}
......@@ -256,7 +261,7 @@ sub read_settingsfile ($$$) {
$design_ref = _rename_import(TESTCONSTMAP, $design_ref);
if (!defined($design_ref)) {
my $msg = "Design constants do not match the FIJI Settings naming scheme.";
my $msg = "Design constants do not match the FIJI Tests naming scheme.";
$logger->error($msg);
return $msg;
}
......@@ -361,6 +366,9 @@ sub read_settingsfile ($$$) {
return $fiji_settings_ref;
}
# Reads a FIJI::Settings file and returns a reference to the object
# Params:
# filename the FIJI::Settings file to be read
sub _read_fiji_cfg ($) {
my $logger = get_logger();
my ($filename) = @_;
......@@ -375,8 +383,8 @@ sub _read_fiji_cfg ($) {
return $global_settings;
}
# generate tailored TESTPATMAP for validating
# test patterns
# generate tailored TESTPATMAP for validating test patterns
# clones the original TESTPATMAP and adds FIU_x_PATTERN_y keys
sub _generate_testpatmap {
my ($self) = @_;
......@@ -818,7 +826,7 @@ sub make_random_test {
my $test = {};
my $global_settings_ref = $self->{'ext'}->{'global_settings'};
# TODO: Move this somewhere else?
# TODO: Move parameter validation somewhere else?
for(my $pi = 0; $pi < $global_settings_ref->{'design'}->{'CFGS_PER_MSG'}; $pi++) {
if($cfg->{'max_duration'}[$pi] < $cfg->{'min_duration'}[$pi]) {
$msg = "Maximum duration ".($pi+1)." must be greater than or equal to minimum duration ".($pi+1);
......
......@@ -86,7 +86,6 @@ sub generate_config_package ($$) {
$logger->debug("=== generate_config_package ===");
$logger->debug(sprintf("%d argument(s)%s", scalar(@_), scalar(@_) > 0 ? ": @_" : ""));
my $fiji_settings = FIJI::Settings->new('download', $fiji_settings_filename);
if (!ref($fiji_settings)) {
return $fiji_settings . " Aborting.\n";
......@@ -94,9 +93,11 @@ sub generate_config_package ($$) {
my $fiji_consts = $fiji_settings->{'design'};
my $fius = $fiji_settings->{'fius'};
# LFSR initial value is given as a 0-padded hex number
my $lfsr_fmt = sprintf("X\"%%0%dx\"",$fiji_consts->{'LFSR_WIDTH'}/4);
my @fiu_configs = ();
# generate the fiu_config record contents
for (my $i = 0; $i < $fiji_consts->{'FIU_NUM'}; $i++) {
my $lfsr_mask = sprintf("$lfsr_fmt",@{$fius}[$i]->{'FIU_LFSR_MASK'});
my $str =<<"END_FIU";
......@@ -110,11 +111,12 @@ END_FIU
my $lfsr_poly_string = sprintf($lfsr_fmt,$fiji_consts->{'LFSR_POLY'});
my $lfsr_seed_string = sprintf($lfsr_fmt,$fiji_consts->{'LFSR_SEED'});
# invert is given as 2-bit binary mask
# need to do this because fault detection invert can be specified even if channel is not enabled
my $invert1 = ($fiji_consts->{'FAULT_DETECT_1_EN'}) ? $fiji_consts->{'FAULT_DETECT_1_INVERT'} : 0;
my $invert2 = ($fiji_consts->{'FAULT_DETECT_2_EN'}) ? $fiji_consts->{'FAULT_DETECT_2_INVERT'} : 0;
my $fault_detect_string = sprintf("%01d%01d",$invert2,$invert1);
my $fiu_configs_string = join(" ,\n",@fiu_configs);
my $vhdl_id = sprintf("X\"%04x\"",$fiji_consts->{'ID'});
my $gentime = localtime;
......@@ -222,7 +224,7 @@ END_VHDL
print $fh $vhdl;
close $fh;
} else {
return "Could not open file '$vhdl_filename' $!";
return "Could not open file '$vhdl_filename' for writing: $!";
}
$logger->info(sprintf("Successfully generated public config package for $fiji_settings_filename in $vhdl_filename.\n"));
......@@ -272,6 +274,7 @@ sub generate_wrapper_module ($) {
my $fiji_inst_name = (defined $fiji_consts->{'FIJI_INST_NAME'}) ? $fiji_consts->{'FIJI_INST_NAME'} : $FIJI_DEFAULTS{'FIJI_INST_NAME'};
my $wrapper_name = (defined $fiji_consts->{'FIJI_WRAPPER_NAME'}) ? $fiji_consts->{'FIJI_WRAPPER_NAME'} : $FIJI_DEFAULTS{'FIJI_WRAPPER_NAME'};
# assign some defaults
my $fiji_clock_signal_name = $FIJI_DEFAULTS{'FIJI_WRAPPER_CLOCK_SIGNAL_NAME'};
my $fiji_original_signal_name = $FIJI_DEFAULTS{'FIJI_WRAPPER_ORIGINAL_SIGNAL_NAME'};
my $fiji_modified_signal_name = $FIJI_DEFAULTS{'FIJI_WRAPPER_MODIFIED_SIGNAL_NAME'};
......@@ -329,7 +332,7 @@ sub generate_wrapper_module ($) {
# add to ports of vhdl component definition
push @dut_comp_ports,(($port->name)." : ".($port->direction)." ".(port2vhdtype($port)));
# if port has assigned a special FIJI function
# check if port has assigned a special FIJI function
if (defined $fiji_porttype) {
if ($fiji_porttype == FIJI_PORTTYPE_CLOCK) {
# clock from DUT to FIJI
......@@ -473,12 +476,12 @@ END_VHDL
}
# genrates a VHDL type declaration for a given port/its net
# generates a VHDL type declaration for a given port/its net
sub port2vhdtype {
my $port = shift(@_);
my $type;
if(!defined $port->net->msb || ($port->net->msb == $port->net->lsb)) {
if(!defined $port->net->msb) {
$type = "std_logic";
} elsif ($port->net->msb > $port->net->lsb) {
$type = sprintf("std_logic_vector(%d downto %d)", $port->net->msb, $port->net->lsb);
......
......@@ -59,6 +59,7 @@ sub Populate {
);
}
# generates a tooltip text for each "pattern block"
sub _hh {
my ($test,$nexttest,$global_settings,$pattern) = @_;
my $duration = "";
......@@ -83,6 +84,7 @@ sub _hh {
return $duration."\n".$fiucfg;
}
# set tests property
sub tests {
my $logger = get_logger();
my ($self, $tests) = @_;
......@@ -102,9 +104,11 @@ sub _populate_widget {
$self->update;
}
# rebuild contents of the widget
sub update {
my $self = shift;
# delete everything drawn on canvas
$self->delete('all');
my $fiji_tests = $self->{'tests'};
......@@ -112,13 +116,18 @@ sub update {
my $total_duration = 0;
my $temp_duration = 0;
my $num_patterns = @{ $fiji_tests->{'tests'}};
# calculate drawing area. need some area for labelling (x/yoff)
my $draw_width = $self->{'width'}-$self->{'xoff'};
my $draw_height = $self->{'height'}-$self->{'yoff'};
# if no repeat, we do not know the length of the last test (with repeat this
# is determined by the duration t1 of the following test
# thus we need some final x space for drawing the last test
if($fiji_tests->{'design'}->{'REPEAT'} == 0) {
$draw_width -= $self->{'xfin'};
}
# calculate the total duration
foreach my $test (@{ $fiji_tests->{'tests'} }) {
my $t1_duration = $test->{'TIMER_VALUE_1'} + 1;
my $t2_duration = $test->{'TIMER_VALUE_2'} + 1;
......@@ -130,17 +139,21 @@ sub update {
$total_duration +=@{ $fiji_tests->{'tests'}}[0]->{'TIMER_VALUE_1'};
}
# calculate the width of a timer value of 0 (actually 1 cycle)
my $xfraction = $draw_width/$total_duration;
my $yfraction = $draw_height/($num_patterns*2);
# init coordinate counters
my $x = $self->{'xoff'};
my $y = $self->{'yoff'};
my $x_base = $self->{'xoff'};
my $y_base = $self->{'yoff'};
# draw x/y axis
$self->createLine(0,$y_base,$self->{'width'},$y_base,-fill=>"black");
$self->createLine($x_base,0,$x_base,$self->{'height'},-fill=>"black");
# init some more loop vars
my $rgbb = 0;
$self->{'helphash'} = {};
my $time = 0;
......@@ -148,8 +161,10 @@ sub update {
my $repend = $x;
my $repy = $y;
# draw all tests
for (my $ti = 0; $ti < @{$fiji_tests->{'tests'}}; $ti++) {
my $rgb = 0;
# with different colors (each color can be 0 or F0
$rgbb = ($rgbb + 1) & 0xF;
$rgb |= (($rgbb & 0x8) > 0) ? 0x808080 : 0x00;
......@@ -161,12 +176,15 @@ sub update {
my $test = @{ $fiji_tests->{'tests'} }[$ti];
my $nexttest;
# check if following test exists
if ($ti < @{$fiji_tests->{'tests'}} -1 ) {
$nexttest = @{ $fiji_tests->{'tests'} }[$ti+1];
} elsif ($fiji_tests->{'design'}->{'REPEAT'} == 1) {
$nexttest = @{ $fiji_tests->{'tests'} }[$fiji_tests->{'design'}->{'REPEAT_OFFSET'}];
}
# some coordinate intermediate vars
my ($x_trigger,$x_pattern_1_start,$y_pattern_1,$x_pattern_2_start,$y_pattern_2,$x_next_pattern_start,$width3);
my $width1 = $xfraction * ($test->{'TIMER_VALUE_1'} + 1);
my $width2 = $xfraction * ($test->{'TIMER_VALUE_2'} + 1);
......@@ -177,6 +195,7 @@ sub update {
$y_pattern_2 = $y_pattern_1 + $yfraction;
$x_trigger = $x_pattern_1_start;
# depending on if there is a next test, draw matching duration or dummy duration
if(!defined ($nexttest)) {
$x_next_pattern_start = $self->{'width'};
$width3 = $x_pattern_2_start - $x_next_pattern_start;
......@@ -185,20 +204,28 @@ sub update {
$x_next_pattern_start = $x_pattern_2_start + $width3;
}
# draw labelling
my $t1 = $self->createText($self->{'xoff'}/2,$y_pattern_1-$yfraction/2,-text=>"$ti:1");
my $t2 = $self->createText($self->{'xoff'}/2,$y_pattern_2-$yfraction/2,-text=>"$ti:2");
# tooltips are kept in a hash with the canvas object ID as key and the text as hash value
$self->{'helphash'}->{$t1} = "Test $ti, Pattern 1";
$self->{'helphash'}->{$t2} = "Test $ti, Pattern 2";
# draw thin dashed horizontal lines framing the entire test
$self->createLine(0,$y_pattern_1,$self->{'width'},$y_pattern_1,-fill=>"black",-dash=>[2,8]);
$self->createLine(0,$y_pattern_2,$self->{'width'},$y_pattern_2,-fill=>"black",-dash=>[6,4]);
# draw thin dashed vertical lines framing each pattern
my $lx1 = $self->createLine($x_pattern_2_start,$y_base,$x_pattern_2_start,$y_pattern_2,-fill=>"black",-dash=>[2,8]);
my $lx2 = $self->createLine($x_next_pattern_start,$y_base,$x_next_pattern_start,$y_pattern_1,-fill=>"black",-dash=>[6,4]);
# if next test does not exist, this pattern is applied "forever".
# express this via dashed border of pattern
my $pattern = ((defined $nexttest && $nexttest->{'TRIGGER'} eq "NONE") ? undef : [6,4]);
# draw a "Waiting" rectange for the duration after downloading, the first test
# until trigger and/or t1 is over
if($ti == 0) {
my $r0 = $self->createRectangle($x_base,$y_base,$x_pattern_1_start,$y_pattern_1,-fill=>"grey",-dash=>$pattern);
my $r0_top = $self->createRectangle($x_base,0,$x_pattern_1_start,$self->{'yoff'}/2,-fill=>"grey");
......@@ -211,16 +238,20 @@ sub update {
$x_trigger = $x;
}
# draw the pattern rectangles
my $r1 = $self->createRectangle($x_pattern_1_start,$y,$x_pattern_2_start,$y_pattern_1,-fill=>"$col");
my $r2 = $self->createRectangle($x_pattern_2_start,$y_pattern_1,$x_next_pattern_start,$y_pattern_2,-fill=>"$col",-dash=>$pattern);
# draw the test rectangle at the top
my $r3 = $self->createRectangle($x_pattern_1_start,0,$x_pattern_1_start+$width2+$width3,$self->{'yoff'}/2,-fill=>"$col");
#BEGIN remove
#BEGIN remove?
# if the top rectangle is clicked, update the edit frame
if(defined $self->{'tf'}) {
$self->bind($r3,'<Button-1>' => sub {$self->{'tf'}->test($test);} );
}
#END remove
#END remove?
# add description text for the patterns as tooltip
$self->{'helphash'}->{$r1} = $self->{'helphash'}->{$t1}."\n"._hh($test,$nexttest,$fiji_tests->{'ext'}->{'global_settings'},1);
$self->{'helphash'}->{$r2} = $self->{'helphash'}->{$t2}."\n"._hh($test,$nexttest,$fiji_tests->{'ext'}->{'global_settings'},2);
......@@ -237,6 +268,7 @@ sub update {
$repy = $y_pattern_1;
}
# calculate timer values & draw them on y axis
$time += $test->{'TIMER_VALUE_2'} + 1;
$self->createText($x_pattern_2_start,$y_base-$self->{'yoff'}/4,-justify=>"left",-text=>($time));
$self->{'helphash'}->{$lx1} = "Time: ".$time;
......@@ -257,6 +289,7 @@ sub update {
$self->{'helphash'}->{$rl1} = "Repeat: ".$fiji_tests->{'design'}->{'REPEAT_OFFSET'}." - END";
}
# attach the tooltip helper widget
$self->{'balloon'}->attach($self, -balloonposition => 'mouse',
-msg => $self->{'helphash'});
......
......@@ -15,6 +15,9 @@
#
# Description:
# FIJI Test Editor Frame
#
# Displays all relevant test data in a frame widget as text entries or drop-down
# menus in a grid
#-------------------------------------------------------------------------------
......@@ -73,6 +76,7 @@ sub Populate {
$self->update();
}
# set a different test as basis
sub test {
my ($self, $test) = @_;
$self->{'test'} = $test;
......@@ -112,9 +116,7 @@ sub _populate_widget ($) {
my $ri = $fi + 1;
$ff->Label(-text=>"FIU $fi")->grid(-column=>0,-row=>($fi+1));
#my $var1;
#my $var2;
$ff->Label(-text=>"FIU $fi")->grid(-column=>0,-row=>($fi+1));
my @optionlist = sort {FIUENUM->{$a} cmp FIUENUM->{$b}} keys(FIUENUM);
$ff->Optionmenu(
......
......@@ -92,9 +92,9 @@ sub main {
# Check mode and execute tests accordingly
if ( $cfg->{'mode'} eq "auto" ) {
$rv = $fiji_downloader->download_auto($cfg->{'port'});
$rv = $fiji_downloader->download_auto($cfg->{'portname'});
} elsif ( $cfg->{'mode'} eq "manual" ) {
$rv = $fiji_downloader->download_manual($cfg->{'port'});
$rv = $fiji_downloader->download_manual($cfg->{'portname'});
} elsif ($cfg->{'mode'} eq "random" ) {
my $new_tests;
my $prob = 0;
......@@ -113,7 +113,7 @@ sub main {
return 1;
} else {
$cfg->{'probabilities'}[FIJI::FIUENUM->{'NONE'}] = 1.0 - $prob;
$rv = $fiji_downloader->download_random($cfg,$new_tests,$cfg->{'port'});
$rv = $fiji_downloader->download_random($cfg,$new_tests,$cfg->{'portname'});
}
} else {
print "$0: Invalid mode \"".$cfg->{'mode'}."\"\n";
......
......@@ -94,6 +94,7 @@ sub main {
my $fiu = @{$settings_ref->{'fius'}}[$fiu_idx];
# split hierarchical net path
my $net_ref = splitnet($fiu->{'FIU_NET_NAME'},$nl->{'nl'});
if(ref($net_ref) ne "HASH") {
......@@ -110,7 +111,6 @@ sub main {
}
# Clock net
$logger->info("Adding CLOCK net");
my $net_ref = splitnet($settings_ref->{'design'}->{'CLOCK_NET'},$nl->{'nl'});
......@@ -125,8 +125,7 @@ sub main {
return 1;
}
# Reset from DUT if enabled
# Instrument reset from DUT if enabled
if($settings_ref->{'design'}->{'RESET_DUT_OUT_EN'} == 1) {
$logger->info("Adding RESET_DUT_OUT net");
my $net_ref = splitnet($settings_ref->{'design'}->{'RESET_DUT_OUT_NAME'},$nl->{'nl'});
......@@ -143,8 +142,7 @@ sub main {
}
}
# Reset to DUT if enabled
# Instrument reset to DUT if enabled
if($settings_ref->{'design'}->{'RESET_DUT_IN_EN'} == 1) {
$logger->info("Adding RESET_DUT_IN net");
my $mod = $nl->{'nl'}->find_module($options->{'toplevel_module'});
......@@ -164,7 +162,7 @@ sub main {
}
$port->userdata(FIJI::VHDL->FIJI_USERDATA_PORTTYPE,FIJI::VHDL->FIJI_PORTTYPE_RESET_TO_DUT);
$nl->{'nl'}->link;
$mod->link;
}
# Trigger from DUT if enabled
......@@ -185,8 +183,7 @@ sub main {
}
}
# FD1 if enabled
# instrument fault detect signal 1 if enabled
if($settings_ref->{'design'}->{'FAULT_DETECT_1_EN'} == 1) {
$logger->info("Adding FAULT_DETECT_1 net");
my $net_ref = splitnet($settings_ref->{'design'}->{'FAULT_DETECT_1_NAME'},$nl->{'nl'});
......@@ -203,8 +200,7 @@ sub main {
}
}
# FD2 if enabled
# instrument fault detect signal 2 if enabled
if($settings_ref->{'design'}->{'FAULT_DETECT_2_EN'} == 1) {
$logger->info("Adding FAULT_DETECT_2 net");
my $net_ref = splitnet($settings_ref->{'design'}->{'FAULT_DETECT_2_NAME'},$nl->{'nl'});
......@@ -309,11 +305,14 @@ sub main {
}
# Takes a net path and extracts the module and net name from it
# Takes a net path and extracts the module and net objects
# params:
# netpath the hierarchical path of the net
# nl the Verilog::Perl netlist