Commit 1af52f1b authored by Stefan Tauner's avatar Stefan Tauner
Browse files

Various demo instruction fixes

parent 1597dbf8
......@@ -37,6 +37,7 @@ include boards/$(BOARD).mk
# Project directories and files
FIJI_PROJECT_DIR=$(FIJI_DIR)/$(FIJI_PROJECT_NAME)
FIJI_OUTPUT_DIR=$(FIJI_PROJECT_DIR)/fiji
FIJI_SYNPLIFY_PROJECT=$(FIJI_PROJECT_DIR)/synp/$(TOPLEVEL_MODULE).prj
MODIFIED_NETLIST_FILE=$(FIJI_OUTPUT_DIR)/$(FILE_PREFIX)_instrumented.$(NETLIST_SUFFIX)
FIJI_CFG_FILE=$(FIJI_OUTPUT_DIR)/fiji.cfg
TEST_FILE=$(FIJI_OUTPUT_DIR)/$(FIJI_PROJECT_NAME).tst
......@@ -56,8 +57,8 @@ all: setup-launch execute-gui
$(FIJI_CFG_FILE): setup-launch
$(ORIGINAL_NETLIST_FILE):
clear
@read -p "Press [Enter] after you synthesized the original netlist to $(ORIGINAL_NETLIST_FILE)..."
clear
# launch the fiji settings editor GUI
setup-launch: $(ORIGINAL_NETLIST_FILE)
......@@ -86,6 +87,7 @@ setup-launch: $(ORIGINAL_NETLIST_FILE)
if [ x"$${skipedit}" != x"s" ]; then \
perl $(PERLFLAGS) $(FIJI_SETUP) --settings=$(FIJI_CFG_FILE) --netlist=$(ORIGINAL_NETLIST_FILE) ; \
fi
clear
# Generate the instrumented netlist and wrapper/config VHDL files
$(MODIFIED_NETLIST_FILE): $(ORIGINAL_NETLIST_FILE) $(FIJI_CFG_FILE)
......@@ -94,6 +96,7 @@ $(MODIFIED_NETLIST_FILE): $(ORIGINAL_NETLIST_FILE) $(FIJI_CFG_FILE)
--netlist=$(ORIGINAL_NETLIST_FILE) \
--file-prefix=$(FILE_PREFIX) \
--output-dir=$(FIJI_OUTPUT_DIR)
@read -p "Instrumentation done. Press [Enter] to continue..."
clear
# Open editor to modify test file
......@@ -104,38 +107,54 @@ $(TEST_FILE):
# Prompt the user to execute the FPGA bitstream
# TODO: Automatization possible?
program-fpga: $(BITSTREAM_FILE)
clear
@read -p "Press [Enter] after you programmed the FPGA..."
# Prompt the user to generate the new Synplify project and display instructions
# on-screen
# TODO: Automatization possible?
define SYNPLIFY_INSTRUCTIONS
Follow these instructions to generate the Synplify project
$(FIJI_DIR)/$(FIJI_SYNPLIFY_PROJECT):
0. Open terminal in $(FIJI_PROJECT_DIR)/synp"
1. Create a new Synplify project *file* named 'spriteflyer_top.prj' in
the respective directory.
2. Open this project (if not done automatically)
endef
$(FIJI_SYNPLIFY_PROJECT):
@echo "Follow these instructions to generate the Synplify project $(FIJI_SYNPLIFY_PROJECT):"
@echo
@echo "0. Open terminal in $(FIJI_PROJECT_DIR)/synp"
@echo
@less $(FIJI_PROJECT_DIR)/synp/README
@echo
@read -p "Press [Enter] when you are ready..."
$(info $(SYNPLIFY_INSTRUCTIONS))
@cat $(FIJI_PROJECT_DIR)/synp/README
@echo "Finally, synthesize the design (F8)."
@read -p "Press [Enter] when Synplify is done and you are ready..."
clear
# Prompt the user to generate the new Quartus project and display instructions
# on-screen
# TODO: Automatization possible?
define PNR_INSTRUCTIONS
Follow these instructions to generate the Place & Route project
$(FIJI_PNR_PROJECT):
@echo "Follow these instructions to generate the Quartus project $(FIJI_PNR_PROJECT):"
@echo
@echo "0. Open terminal in $(FIJI_PROJECT_DIR)/$(FIJI_PNR_DIR)"
@echo
@less $(FIJI_PROJECT_DIR)/$(FIJI_PNR_DIR)/README
@echo
0. Open terminal in $(FIJI_PROJECT_DIR)/$(FIJI_PNR_DIR)
endef
$(FIJI_PNR_PROJECT):
$(info $(PNR_INSTRUCTIONS))
@cat $(FIJI_PROJECT_DIR)/$(FIJI_PNR_DIR)/README
@read -p "Press [Enter] when you are ready..."
# Prompt the user to place&route the modified netlist + wrapper
# TODO: Automatization possible?
$(BITSTREAM_FILE): $(MODIFIED_NETLIST_FILE) $(FIJI_SYNPLIFY_PROJECT) $(FIJI_PNR_PROJECT)
clear
@echo "Place & Route the modified netlist:"
@echo ' in Quartus: "Compile Design"'
@echo ' in Vivado: "Implement Design" and "Generate Bitstream"'
@echo ' in Vivado: "Generate Bitstream"'
@echo
@read -p "Press [Enter] when you are ready..."
......@@ -162,4 +181,9 @@ execute-random: $(BITSTREAM_FILE) $(TEST_FILE) program-fpga
-o=0.2 --port=$(FIJI_PORT)
execute-gui: $(BITSTREAM_FILE) program-fpga
@echo "Launching Executing Engine GUI with pre-defined test sequence..."
perl $(PERLFLAGS) $(FIJI_EXECUTE_GUI) --settings=$(DOWNLOAD_CFG) --tests=$(TEST_FILE)
MAKEFLAGS += --no-builtin-rules
.SUFFIXES:
.PRECIOUS: %.bit %.sof
......@@ -5,6 +5,5 @@ FIJI_PNR_DIR=vivado
NETLIST_SUFFIX=vm
ORIGINAL_NETLIST_FILE=synp/basys3/basys3/spriteflyer_top.vm
FIJI_SYNPLIFY_PROJECT=$(FIJI_PROJECT_NAME)/synp/$(TOPLEVEL_MODULE).prj
FIJI_PNR_PROJECT=$(FIJI_PROJECT_NAME)/$(FIJI_PNR_DIR)/$(FIJI_PROJECT_NAME).xpr
FIJI_PNR_PROJECT=$(FIJI_PROJECT_DIR)/$(FIJI_PNR_DIR)/$(FIJI_PROJECT_NAME).xpr
BITSTREAM_FILE=$(FIJI_PROJECT_DIR)/$(FIJI_PNR_DIR)/$(FIJI_PROJECT_NAME).runs/impl_1/fiji_top.bit
......@@ -5,6 +5,5 @@ FIJI_PNR_DIR=quartus
NETLIST_SUFFIX=vqm
ORIGINAL_NETLIST_FILE=synp/de0/de0/spriteflyer_top.vqm
FIJI_SYNPLIFY_PROJECT=$(FIJI_PROJECT_NAME)/synp/$(TOPLEVEL_MODULE).prj
FIJI_PNR_PROJECT=$(FIJI_PROJECT_NAME)/$(FIJI_PNR_DIR)/$(FIJI_PROJECT_NAME).qpf
BITSTREAM_FILE=$(FIJI_PROJECT_DIR)/$(FIJI_PNR_DIR)/output_files/fiji_top.sof
......@@ -5,6 +5,5 @@ FIJI_PNR_DIR=vivado
NETLIST_SUFFIX=vm
ORIGINAL_NETLIST_FILE=synp/zybo/zybo/spriteflyer_top.vm
FIJI_SYNPLIFY_PROJECT=$(FIJI_PROJECT_NAME)/synp/$(TOPLEVEL_MODULE).prj
FIJI_PNR_PROJECT=$(FIJI_PROJECT_NAME)/$(FIJI_PNR_DIR)/$(FIJI_PROJECT_NAME).xpr
BITSTREAM_FILE=$(FIJI_PROJECT_DIR)/$(FIJI_PNR_DIR)/$(FIJI_PROJECT_NAME).runs/impl_1/fiji_top.bit
; FIJI::ConfigSorted 0.1
; Tue Apr 11 13:35:46 2017
; Tue May 8 18:08:00 2018
[CONSTS]
COMPLETION_SCRIPT=
......@@ -23,6 +23,7 @@ PROB_STUCK_AT_0=0.2
PROB_STUCK_AT_1=0.2
PROB_STUCK_OPEN=0.2
REPEAT=0
REPEAT_NUM=0
REPEAT_OFFSET=0
UART=/dev/ttyDigilent
......@@ -34,19 +35,19 @@ FIU_1_FAULT_2=NONE
FIU_2_FAULT_1=NONE
FIU_2_FAULT_2=NONE
RST_DUT_AFTER_CFG=0
TIMER_VALUE_1=1000000
TIMER_VALUE_1=100000000
TIMER_VALUE_2=100000000
TRIGGER=EXT
[TEST1]
FIU_0_FAULT_1=NONE
FIU_0_FAULT_2=NONE
FIU_1_FAULT_1=STUCK_AT_1
FIU_1_FAULT_1=STUCK_OPEN
FIU_1_FAULT_2=NONE
FIU_2_FAULT_1=NONE
FIU_2_FAULT_2=NONE
RST_DUT_AFTER_CFG=0
TIMER_VALUE_1=1000000
TIMER_VALUE_1=100000000
TIMER_VALUE_2=100000000
TRIGGER=NONE
......@@ -55,11 +56,11 @@ FIU_0_FAULT_1=NONE
FIU_0_FAULT_2=NONE
FIU_1_FAULT_1=NONE
FIU_1_FAULT_2=NONE
FIU_2_FAULT_1=NONE
FIU_2_FAULT_2=STUCK_OPEN
FIU_2_FAULT_1=STUCK_OPEN
FIU_2_FAULT_2=NONE
RST_DUT_AFTER_CFG=0
TIMER_VALUE_1=1000000
TIMER_VALUE_2=1000000
TIMER_VALUE_1=100000000
TIMER_VALUE_2=100000000
TRIGGER=NONE
1. Create a new Synplify project file named 'spriteflyer_top.prj'
2. Open the project
3. Rename the default implementation to 'basys3' and enter the following settings:
Device: Xilinx Artix xc7a35t-cpg236
Use Vivado: YES
Device: Xilinx Artix7 XC7A35T-CPG236-1
Result Base Name: spriteflyer_top
Output Format: VM
Output Filename: spriteflyer_top.vm
Use Vivado: YES
Verilog top-level module: fiji_top
4. Add the following files to the project:
../fiji/tmr_vga_demo_instrumented.vqm
../fiji/tmr_vga_demo_instrumented.vm
../fiji/tmr_vga_demo_config_pkg.vhd
../fiji/tmr_vga_demo_wrapper.vhd
../fiji/tmr_vga_demo_constraints.synplify.fdc
......@@ -22,3 +18,4 @@
The constraints have already been entered for this demo.
In a 'real' flow, they have to be manually transferred from
the original Synplify project
1. Create a new Vivado post-synthesis project in the 'vivado' directory named 'basys3_test_1.xpr'
1. Create a new Vivado post-synthesis project in the 'vivado' directory
named 'basys3_test_1.xpr'
Add Source:
../synp/basys3/spriteflyer_top.vm as source
Add Constraints files:
../fiji/tmr_vga_demo_constraints.vivado.xdc
../../../boards/pins_basys3.xdc
./pins_fiji.xdc
./fiji_pins.xdc
./clock.xdc
The pin and clock constraints have already been added in this demo.
In a 'real' flow, these would have to be manually transferred or
entered.
Set xc7a35tcpg236-1 as device
Set xc7a35tcpg236-1 as device
Set fiji_top as top-level module
Set fiji_top as top-level module
2. Check that all imported files - especially the constraints - were
imported correctly.
2. Check pin and clock constraints
3. Execute "Run Implementation"
3. Run implementation and generate bitstream
; FIJI::ConfigSorted 0.1
; Thu Sep 7 16:36:10 2017
; Tue May 8 18:08:00 2018
[CONSTS]
COMPLETION_SCRIPT=
FIJI_CFG=fiji.cfg
HALT_ON_CRC_ERROR=1
HALT_ON_FAULT_DETECT=1
HALT_ON_FAULT_DETECT=0
HALT_ON_ID_ERROR=1
HALT_ON_UART_ERROR=1
HALT_ON_UNDERRUN=0
INITIAL_RESET=0
INITIAL_TRIGGER=NONE
MAX_DUR_T1=5000000
MAX_DUR_T2=5000000
MIN_DUR_T1=500000
MIN_DUR_T2=500000
INITIAL_TRIGGER=EXT
MAX_DUR_T1=50000000
MAX_DUR_T2=50000000
MIN_DUR_T1=10000000
MIN_DUR_T2=10000000
MULTIFAULT=1
NUM_TESTS=1
PROB_DELAY=0.1
PROB_SEU=0.1
PROB_STUCK_AT_0=0.1
PROB_STUCK_AT_1=0.1
PROB_STUCK_OPEN=0.1
NUM_TESTS=3
PROB_DELAY=0.2
PROB_SEU=0.2
PROB_STUCK_AT_0=0.2
PROB_STUCK_AT_1=0.2
PROB_STUCK_OPEN=0.2
REPEAT=0
REPEAT_NUM=0
REPEAT_OFFSET=0
UART=/dev/ttyUSB1
UART=/dev/ttyDigilent
[TEST0]
FIU_0_FAULT_1=NONE
FIU_0_FAULT_1=STUCK_OPEN
FIU_0_FAULT_2=NONE
FIU_1_FAULT_1=NONE
FIU_1_FAULT_2=NONE
FIU_2_FAULT_1=NONE
FIU_2_FAULT_2=NONE
RST_DUT_AFTER_CFG=0
TIMER_VALUE_1=500000
TIMER_VALUE_2=500000
TIMER_VALUE_1=50000000
TIMER_VALUE_2=50000000
TRIGGER=EXT
[TEST1]
FIU_0_FAULT_1=NONE
FIU_0_FAULT_2=NONE
FIU_1_FAULT_1=STUCK_OPEN
FIU_1_FAULT_2=NONE
FIU_2_FAULT_1=NONE
FIU_2_FAULT_2=NONE
RST_DUT_AFTER_CFG=0
TIMER_VALUE_1=50000000
TIMER_VALUE_2=50000000
TRIGGER=NONE
[TEST2]
FIU_0_FAULT_1=NONE
FIU_0_FAULT_2=NONE
FIU_1_FAULT_1=NONE
FIU_1_FAULT_2=NONE
FIU_2_FAULT_1=STUCK_OPEN
FIU_2_FAULT_2=NONE
RST_DUT_AFTER_CFG=0
TIMER_VALUE_1=50000000
TIMER_VALUE_2=50000000
TRIGGER=NONE
......@@ -4,22 +4,25 @@
../../../synp/de0/de0/spriteflyer_top_p_sprite_rom_s_spritmif1.hex
../../../synp/de0/de0/spriteflyer_top_p_sprite_rom_s_spritmif2.hex
2. Create a new project named 'de0_test_1.qpf'
2. Start Quartus and create a new project named 'de0_test_1.qpf'
Set Cyclone III - EP3C16-F484-C6 as device
Set fiji_top as top-level entity
3. Add the following files to the project
../synp/de0/spriteflyer_top.vqm
../fiji/tmr_vga_demo_constraints.quartus.qsf
./fiji_top.sdc
4. Import the assignments from
4. Set Cyclone III - EP3C16-F484-C6 as device
5. Import the assignments from
../../../boards/pins_de0.qsf
./fiji_pins.qsf
The clock and pin constraints have already been entered for this demo.
In a 'real' project, you would have to manually enter them in Quartus.
5. Perform 'Analysis and Synthesis'
6. Perform 'Analysis and Synthesis'
7. Check the imported pin assignments in the Pin Planner
6. Check the imported pin assignments in the Pin Planner
; FIJI::ConfigSorted 0.1
; Mon May 7 17:26:11 2018
; Tue May 8 18:08:00 2018
[CONSTS]
COMPLETION_SCRIPT=
FIJI_CFG=fiji.cfg
HALT_ON_CRC_ERROR=1
HALT_ON_FAULT_DETECT=1
HALT_ON_FAULT_DETECT=0
HALT_ON_ID_ERROR=1
HALT_ON_UART_ERROR=1
HALT_ON_UNDERRUN=0
INITIAL_RESET=0
INITIAL_TRIGGER=NONE
MAX_DUR_T1=12500000
MAX_DUR_T2=12500000
MIN_DUR_T1=1250000
MIN_DUR_T2=1250000
INITIAL_TRIGGER=EXT
MAX_DUR_T1=125000000
MAX_DUR_T2=125000000
MIN_DUR_T1=10000000
MIN_DUR_T2=10000000
MULTIFAULT=1
NUM_TESTS=3
PROB_DELAY=0.1
PROB_SEU=0.1
PROB_STUCK_AT_0=0.1
PROB_STUCK_AT_1=0.1
PROB_STUCK_OPEN=0.1
PROB_DELAY=0.2
PROB_SEU=0.2
PROB_STUCK_AT_0=0.2
PROB_STUCK_AT_1=0.2
PROB_STUCK_OPEN=0.2
REPEAT=0
REPEAT_NUM=0
REPEAT_OFFSET=0
UART=
UART=/dev/ttyDigilent
[TEST0]
FIU_0_FAULT_1=NONE
FIU_0_FAULT_1=STUCK_OPEN
FIU_0_FAULT_2=NONE
FIU_1_FAULT_1=NONE
FIU_1_FAULT_2=NONE
FIU_2_FAULT_1=NONE
FIU_2_FAULT_2=NONE
RST_DUT_AFTER_CFG=0
TIMER_VALUE_1=1250000
TIMER_VALUE_2=1250000
TRIGGER=NONE
TIMER_VALUE_1=125000000
TIMER_VALUE_2=125000000
TRIGGER=EXT
[TEST1]
FIU_0_FAULT_1=NONE
FIU_0_FAULT_2=NONE
FIU_1_FAULT_1=NONE
FIU_1_FAULT_1=STUCK_OPEN
FIU_1_FAULT_2=NONE
FIU_2_FAULT_1=NONE
FIU_2_FAULT_2=NONE
RST_DUT_AFTER_CFG=0
TIMER_VALUE_1=1250000
TIMER_VALUE_2=1250000
TIMER_VALUE_1=125000000
TIMER_VALUE_2=125000000
TRIGGER=NONE
[TEST2]
......@@ -56,11 +56,11 @@ FIU_0_FAULT_1=NONE
FIU_0_FAULT_2=NONE
FIU_1_FAULT_1=NONE
FIU_1_FAULT_2=NONE
FIU_2_FAULT_1=NONE
FIU_2_FAULT_1=STUCK_OPEN
FIU_2_FAULT_2=NONE
RST_DUT_AFTER_CFG=0
TIMER_VALUE_1=1250000
TIMER_VALUE_2=1250000
TIMER_VALUE_1=125000000
TIMER_VALUE_2=125000000
TRIGGER=NONE
1. Create a new Synplify project file named 'spriteflyer_top.prj'
3. Rename the default implementation to 'basys3' and enter the following settings:
2. Open the project
3. Rename the default implementation to 'de0' and enter the following settings:
Device: Zynq 7010 xc7z010-clg400-1
Use Vivado: YES
Device: Zynq 7010 XC7Z010-CLG400-1
Result Base Name: spriteflyer_top
Output Format: VM
Output Filename: spriteflyer_top.vm
Use Vivado: YES
Verilog top-level module: fiji_top
4. Add the following files to the project:
../fiji/tmr_vga_demo_instrumented.vqm
../fiji/tmr_vga_demo_instrumented.vm
../fiji/tmr_vga_demo_config_pkg.vhd
../fiji/tmr_vga_demo_wrapper.vhd
../fiji/tmr_vga_demo_constraints.synplify.fdc
......@@ -21,4 +17,5 @@
The constraints have already been entered for this demo.
In a 'real' flow, they have to be manually transferred from
the original Synplify project
\ No newline at end of file
the original Synplify project
1. Create a new Vivado project named 'zybo_test_1.xpr'
1. Create a new Vivado post-synthesis project in the 'vivado' directory
named 'zybo_test_1.xpr'
Set xc7z010-clg400-1 as device
Add Source:
../synp/zybo/spriteflyer_top.vm as source
Add Constraints files:
../fiji/tmr_vga_demo_constraints.vivado.xdc
../../../boards/pins_zybo.xdc
./pins_fiji.xdc
./fiji_pins.xdc
./clock.xdc
The pin and clock constraints have already been added in this demo.
In a 'real' flow, these would have to be manually transferred or
entered.
2. Run Synthesis
Set xc7z010-clg400-1 as device
Set fiji_top as top-level module
2. Check that all imported files - especially the constraints - were
imported correctly.
3. Check pin and clock constraints
3. Execute "Run Implementation"
4. Run implementation and generate bitstream
\ No newline at end of file
......@@ -19,8 +19,8 @@ engine can be seen on the right side.
The use case is designated for use with the Cyclone III-based DE0 development
board from Terasic\footnote{\url{http://de0.terasic.com.tw}, visited on May~7, 2018},
the Artix~7-based Basys~3\footnote{\url{https://reference.digilentinc.com/reference/programmable-logic/basys-3/start}, visited on May~7, 2017},
or the Zynq~7000-based Zybo\footnote{\url{https://reference.digilentinc.com/reference/programmable-logic/zybo/start}, visited on May~7, 2017},
the Artix~7-based Basys~3\footnote{\url{https://reference.digilentinc.com/reference/programmable-logic/basys-3/start}, visited on May~7, 2018},
or the Zynq~7000-based Zybo\footnote{\url{https://reference.digilentinc.com/reference/programmable-logic/zybo/start}, visited on May~7, 2018},
but is portable to other boards providing a \ac{VGA} connector with little effort. It is implemented in VHDL.
\begin{figure}[htb]
......@@ -43,6 +43,7 @@ Thus, faults affecting the direction register will cause the domain 0 to permane
In a real-world design the states of the redundant units would usually be determined by the voter.
\subsection{Hardware Setup}
\label{sec:hardware_setup}
\subsubsection{Digilent Basys 3}
\begin{itemize}
......@@ -161,7 +162,13 @@ The resulting file should be located in the \texttt{synp} directory (e.g., \text
\subsubsection{Run setup}
A pre-configured settings file for \ac{FIJI} is located in \texttt{fiji/de0\_test\_1/fiji/fiji.cfg}.
To review the configuration you can open it up in the \ac{FIJI} Setup GUI:
It targets three nets in the first sprite engine (TMR1) that directly influence the~\ldots
\begin{itemize}
\item sprite content,
\item plane direction, and
\item output of the red color channel.
\end{itemize}
To review and edit the configuration you can open it up in the \ac{FIJI} Setup GUI:
\begin{lstlisting}[style=shell,gobble=8]
$ perl ../../../bin/fiji_setup.pl -s fiji/de0_test_1/fiji/fiji.cfg \
-n synp/de0/de0/spriteflyer_top.vqm
......@@ -202,7 +209,7 @@ The resulting file should be located in the \texttt{synp} directory (e.g., \text
Finally, you have also to set the correct device in the first tab:
\begin{itemize}
\item \textbf{Basys~3}: Artix7 XC7A35T-CPG236-1
\item \textbf{DE0}: Cyclone III EP3C16-F484-C6
\item \textbf{DE0}: Cyclone III EP3C16-FC484-6 (EP3C16-F484-C6)
\item \textbf{Zybo}: Zynq XC7Z010-CLG400-1
\end{itemize}
......@@ -233,9 +240,9 @@ To create the final bitstream for Altera FPGAs the instrumented netlist needs to
synp/de0/de0/spriteflyer_top_p_sprite_rom_s_spritmif2.hex
\end{plainlisting}
\item Create a new project (e.g., \texttt{fiji\_de0.qpf} in \texttt{fiji/de0\_test\_1/quartus}
\item Create a new project (e.g., \texttt{fiji\_de0.qpf} in \texttt{fiji/de0\_test\_1/quartus})
Set Cyclone III - EP3C16-F484-C6 as device
Set \texttt{fiji\_top} as top-level entity.
\item Add the following files to the project
\begin{plainlisting}[gobble=12]
......@@ -244,6 +251,8 @@ To create the final bitstream for Altera FPGAs the instrumented netlist needs to
fiji/de0_test_1/quartus/fiji_top.sdc
\end{plainlisting}
\item Set the device to Cyclone III - EP3C16-F484-C6.
\item Import the assignments from
\begin{plainlisting}[gobble=12]
boards/pins_de0.qsf
......@@ -311,12 +320,6 @@ Replace `basys3` with your board name where applicable.
$ perl ../../../bin/fiji_ee_gui.pl -s fiji/de0_test_1/fiji/tmr_vga_demo_download.cfg
\end{lstlisting}
\item Execute tests at will
% \item Execute tests:
% \begin {itemize}
% \item Pre-defined sequence in \texttt{fiji/de0\_test\_1/fiji/tmr\_vga\_demo\_test.tst}
% \item Manual tests
% \item Random tests
% \end {itemize}
\end{enumerate}
When the \emph{\ac{TMR} Enable} switch is in ``0'' position, the output from
......@@ -328,3 +331,7 @@ generated by majority voting over the three \ac{TMR} domains. Faults in \ac{TMR}
domain 0 are masked and thus are not visible. When \ac{TMR} is enabled, the LEDs on
the board show (1) if an error is detected by the voter (one domain disagrees
with the others) and (2) in which voter (Red, Green, Blue) the error is detected.
There exists a pre-defined sequence in \texttt{fiji/de0\_test\_1/fiji/tmr\_vga\_demo\_test.tst}.
Its first test pattern waits for the external trigger (which is mapped to a button, see~\cref{sec:hardware_setup}).
When this fires a stuck-open fault is injected for one second in each of the three instrumented nets respectively with one fault-free second in-between.
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