Commit 192a4623 authored by Stefan Tauner's avatar Stefan Tauner
Browse files

netlist: fix some bugs for re-instrumented vectors with assignments

Covered in testcase_ASSIGN_PIN_bus_bus2single
parent 31d4d679
......@@ -636,6 +636,8 @@ sub instrument_net {
# Retrieve net object of LHS of the assignment to determine if it is a bus and if the assignment is to the complete net or a single bit.
my $lhs_elems = $self->_extract_netstring_elements($connection->lhs);
my $lhs_net_name = $lhs_elems->{'net_name'};
my $lhs_net_msb = $lhs_elems->{'msb'};
my $lhs_net_lsb = $lhs_elems->{'lsb'};
my $lhs_net = $mod->find_net($lhs_net_name);
if (!defined($lhs_net)) {
my $lhs_port = $mod->find_port($lhs_net_name);
......@@ -653,13 +655,12 @@ sub instrument_net {
$driver_bit = $connection->userdata->{'fiji_driver_bit'};
}
if (!defined($net_tmp) || !defined($net_tmp->userdata("first_instrumented_bit"))) {
$logger->debug("Connecting to intermediate net \"" . $net_name_tmp . "\" the continuous assignment of \"" . $connection->rhs . "\"");
# need to remember what was originally connected to this assign
# to instrument two nets driven by one assign
$connection->userdata('former_assign' => {'lhs' => $connection->lhs, 'rhs' => $connection->rhs});
$connection->lhs($net_name_tmp);
}
my $indices = ($driver_is_vector && defined($lhs_net_msb)) ? "[$lhs_net_msb:$lhs_net_lsb]" : "";
$logger->debug("Connecting to intermediate net \"$net_name_tmp$indices\" the continuous assignment of \"" . $connection->rhs . "\"");
# need to remember what was originally connected to this assign
# to instrument two nets driven by one assign
$connection->userdata('former_assign' => {'lhs' => $connection->lhs, 'rhs' => $connection->rhs});
$connection->lhs($net_name_tmp.$indices);
} else {
$logger->error("Driver instance is neither pin, port nor contassign?");
......@@ -718,8 +719,8 @@ sub instrument_net {
$logger->fatal($msg);
return $msg;
} elsif (ref($prev_driver) eq "Verilog::Netlist::ContAssign") {
$logger->debug(" reassigning ContAssign \"" . $prev_driver->lhs . " = " . $prev_driver->rhs . "\"");
$prev_driver->rhs($net_name_tmp."[".$prev_bit."]");
$logger->debug(" reassigning ContAssign \"" . $prev_driver->lhs . " --> \"".$net_name_tmp."[".$prev_bit."]\" = ". $prev_driver->rhs . "\" ");
$prev_driver->lhs($net_name_tmp."[".$prev_bit."]");
}
# And add the default assignments of the (possibly yet) uninstrumented bits
......
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