Yosys/HX8K Demo: Add FIJI "logo"

docs/demos/tinyvga/impl/fiji/fiji.cfg

 ; FIJI::ConfigSorted 0.1
-; Wed Sep 13 15:57:41 2017
+; Sat Sep 16 17:07:22 2017
 
 [CONSTS]
 BAUDRATE=115200
@@ -43,7 +43,7 @@ TRIG_EXT_IN_NAME=s_fiji_trig_ext_i
 TX_OUT_NAME=s_fiji_tx_o
 
 [FIU0]
-DRIVER_PATH="tinyvga/_535_/Q"
+DRIVER_PATH="tinyvga/_734_/Q"
 DRIVER_TYPE=PIN
 FAULT_MODEL=RUNTIME
 LFSR_MASK=0x10
@@ -51,7 +51,7 @@ NAME=
 NET_NAME="tinyvga/green[3]"
 
 [FIU1]
-DRIVER_PATH="tinyvga/_531_/Q"
+DRIVER_PATH="tinyvga/_730_/Q"
 DRIVER_TYPE=PIN
 FAULT_MODEL=RUNTIME
 LFSR_MASK=0x20
@@ -59,7 +59,7 @@ NAME=
 NET_NAME="tinyvga/red[3]"
 
 [FIU2]
-DRIVER_PATH="tinyvga/_539_/Q"
+DRIVER_PATH="tinyvga/_738_/Q"
 DRIVER_TYPE=PIN
 FAULT_MODEL=RUNTIME
 LFSR_MASK=0x40
@@ -67,7 +67,7 @@ NAME=
 NET_NAME="tinyvga/blue[3]"
 
 [FIU3]
-DRIVER_PATH="tinyvga/_544_/Q"
+DRIVER_PATH="tinyvga/_743_/Q"
 DRIVER_TYPE=PIN
 FAULT_MODEL=RUNTIME
 LFSR_MASK=0x20
@@ -75,7 +75,7 @@ NAME=
 NET_NAME="tinyvga/memcol_off[4]"
 
 [FIU4]
-DRIVER_PATH="tinyvga/_549_/Q"
+DRIVER_PATH="tinyvga/_748_/Q"
 DRIVER_TYPE=PIN
 FAULT_MODEL=RUNTIME
 LFSR_MASK=0x40

docs/demos/tinyvga/rtl/tinyvga.v

@@ -29,6 +29,10 @@ module tinyvga (input  osc,
     reg  [7:0]  frame_cnt;
     wire [7:0]  frame_cnt_next;
 
+    // Logo
+    reg  [6:0]  logocol;
+    reg  [5:0]  logoln;
+
     ////////////////////////////////////////////////////////////////////
 
     pll pll_i(.clock_in(osc),.clock_out(clk36m),.locked(locked));
@@ -59,11 +63,15 @@ module tinyvga (input  osc,
             memln        <= 6'h0;
             frame_cnt    <= 8'b0;
             led          <= 8'b0;
+            logocol      <= 8'b0;
+            logoln       <= 7'b0;
         end else begin
-            column <= column_next[9:0];
-            memcol <= column[7:1] + memcol_off;
-            memln  <= line[6:1] + memln_off;
-            led    <= frame_cnt;
+            column  <= column_next[9:0];
+            memcol  <= column[7:1] + memcol_off;
+            memln   <= line[6:1] + memln_off;
+            led     <= frame_cnt;
+            logocol <= column[9:2] - 8'd36;
+            logoln  <= line[7:2] - 7'd43;
 
             if (column == 823)
                 hsync <= 1'b1;
@@ -111,22 +119,38 @@ module tinyvga (input  osc,
     reg [11:0] imem [8191:0];
     reg [11:0] memline;
 
-    initial
-        $readmemh("color.mem",imem);
+    reg [1:0] logo[8191:0];
+    reg [1:0] logoline;
 
+    initial begin
+        $readmemh("color.mem",imem);
+        $readmemb("logo.mem",logo);
+    end
 
     always @(posedge clk36m) begin
         if (reset) begin
-            red     <= 4'b0;
-            green   <= 4'b0;
-            blue    <= 4'b0;
-            memline <= 12'b0;
+            red      <= 4'b0;
+            green    <= 4'b0;
+            blue     <= 4'b0;
+            memline  <= 12'b0;
+            logoline <= 2'b0;
         end else begin
             memline = imem[{memln,memcol}];
+            logoline = logo[{logoln,logocol}];
             if (blank) begin
                 red   <= 4'b0;
                 green <= 4'b0;
                 blue  <= 4'b0;
+            end else if (logoline > 2'b0 && line > 171 && line < 428 && column > 143 && column < 656) begin
+                if (logoline == 2'b01) begin
+                    red   <= {2'b0,memline[11:10]};
+                    green <= {2'b0,memline[7:6]};
+                    blue  <= {2'b0,memline[3:2]};
+                end else begin
+                    red   <= {logoline[0],memln_off[4:2]};
+                    green <= {logoline[0],memln_off[4:2]};
+                    blue  <= {logoline[0],memln_off[4:2]};
+                end
             end else begin
                 red   <= memline[11:8];
                 green <= memline[7:4];

docs/demos/tinyvga/sim/logo.mem

+../impl/original/logo.mem
\ No newline at end of file