Added tst files for TMR demo

docs/demos/tmr_vga/fiji/basys3_test_1/fiji/basys3_test_1.tst

+; FIJI::ConfigSorted 0.1
+; Tue Apr 11 13:35:46 2017
+
+[CONSTS]
+COMPLETION_SCRIPT=
+FIJI_CFG=fiji.cfg
+HALT_ON_CRC_ERROR=1
+HALT_ON_FAULT_DETECT=0
+HALT_ON_ID_ERROR=1
+HALT_ON_UART_ERROR=1
+HALT_ON_UNDERRUN=0
+INITIAL_RESET=0
+INITIAL_TRIGGER=EXT
+MAX_DUR_T1=100000000
+MAX_DUR_T2=100000000
+MIN_DUR_T1=10000000
+MIN_DUR_T2=10000000
+MULTIFAULT=1
+NUM_TESTS=3
+PROB_DELAY=0.2
+PROB_SEU=0.2
+PROB_STUCK_AT_0=0.2
+PROB_STUCK_AT_1=0.2
+PROB_STUCK_OPEN=0.2
+REPEAT=0
+REPEAT_OFFSET=0
+UART=/dev/ttyDigilent
+
+[TEST0]
+FIU_0_FAULT_1=STUCK_OPEN
+FIU_0_FAULT_2=NONE
+FIU_1_FAULT_1=NONE
+FIU_1_FAULT_2=NONE
+FIU_2_FAULT_1=NONE
+FIU_2_FAULT_2=NONE
+RST_DUT_AFTER_CFG=0
+TIMER_VALUE_1=1000000
+TIMER_VALUE_2=100000000
+TRIGGER=EXT
+
+[TEST1]
+FIU_0_FAULT_1=NONE
+FIU_0_FAULT_2=NONE
+FIU_1_FAULT_1=STUCK_AT_1
+FIU_1_FAULT_2=NONE
+FIU_2_FAULT_1=NONE
+FIU_2_FAULT_2=NONE
+RST_DUT_AFTER_CFG=0
+TIMER_VALUE_1=1000000
+TIMER_VALUE_2=100000000
+TRIGGER=NONE
+
+[TEST2]
+FIU_0_FAULT_1=NONE
+FIU_0_FAULT_2=NONE
+FIU_1_FAULT_1=NONE
+FIU_1_FAULT_2=NONE
+FIU_2_FAULT_1=NONE
+FIU_2_FAULT_2=STUCK_OPEN
+RST_DUT_AFTER_CFG=0
+TIMER_VALUE_1=1000000
+TIMER_VALUE_2=1000000
+TRIGGER=NONE
+
+

docs/demos/tmr_vga/fiji/de0_test_1/fiji/de0_test_1.tst

+; FIJI::ConfigSorted 0.1
+; Thu Sep  7 16:36:10 2017
+
+[CONSTS]
+COMPLETION_SCRIPT=
+FIJI_CFG=fiji.cfg
+HALT_ON_CRC_ERROR=1
+HALT_ON_FAULT_DETECT=1
+HALT_ON_ID_ERROR=1
+HALT_ON_UART_ERROR=1
+HALT_ON_UNDERRUN=0
+INITIAL_RESET=0
+INITIAL_TRIGGER=NONE
+MAX_DUR_T1=5000000
+MAX_DUR_T2=5000000
+MIN_DUR_T1=500000
+MIN_DUR_T2=500000
+MULTIFAULT=1
+NUM_TESTS=1
+PROB_DELAY=0.1
+PROB_SEU=0.1
+PROB_STUCK_AT_0=0.1
+PROB_STUCK_AT_1=0.1
+PROB_STUCK_OPEN=0.1
+REPEAT=0
+REPEAT_NUM=0
+REPEAT_OFFSET=0
+UART=/dev/ttyUSB1
+
+[TEST0]
+FIU_0_FAULT_1=NONE
+FIU_0_FAULT_2=NONE
+FIU_1_FAULT_1=NONE
+FIU_1_FAULT_2=NONE
+FIU_2_FAULT_1=NONE
+FIU_2_FAULT_2=NONE
+RST_DUT_AFTER_CFG=0
+TIMER_VALUE_1=500000
+TIMER_VALUE_2=500000
+TRIGGER=NONE
+
+

docs/demos/tmr_vga/fiji/zybo_test_1/fiji/zybo_test_1.tst

+; FIJI::ConfigSorted 0.1
+; Mon May  7 17:26:11 2018
+
+[CONSTS]
+COMPLETION_SCRIPT=
+FIJI_CFG=fiji.cfg
+HALT_ON_CRC_ERROR=1
+HALT_ON_FAULT_DETECT=1
+HALT_ON_ID_ERROR=1
+HALT_ON_UART_ERROR=1
+HALT_ON_UNDERRUN=0
+INITIAL_RESET=0
+INITIAL_TRIGGER=NONE
+MAX_DUR_T1=12500000
+MAX_DUR_T2=12500000
+MIN_DUR_T1=1250000
+MIN_DUR_T2=1250000
+MULTIFAULT=1
+NUM_TESTS=3
+PROB_DELAY=0.1
+PROB_SEU=0.1
+PROB_STUCK_AT_0=0.1
+PROB_STUCK_AT_1=0.1
+PROB_STUCK_OPEN=0.1
+REPEAT=0
+REPEAT_NUM=0
+REPEAT_OFFSET=0
+UART=
+
+[TEST0]
+FIU_0_FAULT_1=NONE
+FIU_0_FAULT_2=NONE
+FIU_1_FAULT_1=NONE
+FIU_1_FAULT_2=NONE
+FIU_2_FAULT_1=NONE
+FIU_2_FAULT_2=NONE
+RST_DUT_AFTER_CFG=0
+TIMER_VALUE_1=1250000
+TIMER_VALUE_2=1250000
+TRIGGER=NONE
+
+[TEST1]
+FIU_0_FAULT_1=NONE
+FIU_0_FAULT_2=NONE
+FIU_1_FAULT_1=NONE
+FIU_1_FAULT_2=NONE
+FIU_2_FAULT_1=NONE
+FIU_2_FAULT_2=NONE
+RST_DUT_AFTER_CFG=0
+TIMER_VALUE_1=1250000
+TIMER_VALUE_2=1250000
+TRIGGER=NONE
+
+[TEST2]
+FIU_0_FAULT_1=NONE
+FIU_0_FAULT_2=NONE
+FIU_1_FAULT_1=NONE
+FIU_1_FAULT_2=NONE
+FIU_2_FAULT_1=NONE
+FIU_2_FAULT_2=NONE
+RST_DUT_AFTER_CFG=0
+TIMER_VALUE_1=1250000
+TIMER_VALUE_2=1250000
+TRIGGER=NONE
+
+