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# HX8K Demo for FIJI+Yosys #

## Prerequisites ##

* Yosys, Arachne-PNR, icepack
* (sadly) Synplify as the VHDL frontend
* FIJI (+environment variable `$FIJI_ROOT` pointing to the checked-out FIJI directory)
* Configuration of Synplify in `impl/instrumented/Makefile`

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## HW Setup ##

1. To control FIJI, the HX8K Breakout Board's FTDI is used. Install the following udev rule:

        SUBSYSTEM=="tty",ATTRS{idVendor}=="0403",ATTRS{idProduct}=="6010",ATTRS{product}=="Lattice FTUSB Interface Cable", SYMLINK+="ttyHX8K"
2. Connect a VGA DAC to the HX8K breakout board, e.g. a XESS StickIt VGA module
   The pin mappings can be found in `impl/original/tinyvga.pcf`. On the XESS
   module, pin `red[3]` maps to R4, `blue[3]` to B4, etc. R0 and G0 are not
   used and may be left unconnected.

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## FIJI Flow ##

1. Carry out the initial synthesis step to obtain a netlist & configure
   FIJI by executing

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        $ make fiji-instrument
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   in `impl/original`

2. Perform the second synthesis step by running

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        $ make prog && make fiji-launch
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   in `impl/instrumented`

3. Inject & observe faults using the FIJI EE GUI

## Non-FIJI Flow ##

To just implement & download the original hardware, just run

    $ make prog
in `impl/original`

## Simulation ##

To simulate the design for a few frames, run

    $ make
in `sim`. Not much automated checking done here...

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## HW Details ##

`tinyvga.imem` is an on-chip memory that holds a 128x64 image defined by
`impl/original/color.mem`.

`tinyvga.sinetab` controls the motion of the image(s) and is defined by
`impl/original/sinetab.mem`.