fault_injection_unit_tb.vhd 10.9 KB
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-- Fault InJection Instrumenter (FIJI)
-- https://embsys.technikum-wien.at/projects/vecs/fiji
--
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-- The creation of this file has been supported by the publicly funded
-- R&D project Josef Ressel Center for Verification of Embedded Computing
-- Systems (VECS) managed by the Christian Doppler Gesellschaft (CDG).
--
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-- Authors:
-- Christian Fibich <fibich@technikum-wien.at>
-- Stefan Tauner <tauner@technikum-wien.at>
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--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable
-- law or agreed to in writing, software, hardware and materials
-- distributed under this License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either expressed or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- See the LICENSE file for more details.
--
-- Description:
--  Fault injection unit testbench file
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--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

library std;
use std.textio.all;

library work;
use work.fault_injection_unit_pkg.all;
use work.fault_selection_type_pkg.all;
use work.public_config_pkg.all;
use work.private_config_pkg.all;
-------------------------------------------------------------------------------

entity fault_injection_unit_tb is
  generic (
    g_seed1          : positive := 42;
    g_seed2          : positive := 4711;
    g_inter_bit_time : time     := 1 us;
    g_inject_time    : time     := 20 us;
    g_data_file_name : string   := "fault_injection_unit_testfile.txt"
    );

end entity fault_injection_unit_tb;

-------------------------------------------------------------------------------

architecture sim of fault_injection_unit_tb is

  constant c_number_fius : natural := 8;

  -- component ports
  signal s_clk_i             : std_logic := '1';
  signal s_reset_n_i         : std_logic;
  signal s_shift_enable_i    : std_logic;
  signal s_lfsr_i            : std_logic_vector(c_lfsr_width-1 downto 0);
  signal s_injection_start_i : std_logic;
  signal s_update_i          : std_logic;
  signal s_original_i        : std_logic_vector(c_number_fius-1 downto 0);
  signal s_modified_o        : std_logic_vector(c_number_fius-1 downto 0);
  signal s_select_pattern_i  : std_logic_vector(c_pattern_bits-1 downto 0);

  signal s_fiu_connector : std_logic_vector(7 downto 0);

  signal s_data_bit : std_logic;


  procedure wait_clock_cycles (
    signal clk     : in std_logic;
    constant LEVEL : in std_logic;
    constant N     : in positive) is
  begin
    for i in 1 to N loop
      wait until clk = LEVEL;
    end loop;
  end procedure wait_clock_cycles;

begin  -- architecture sim

  -- component instantiation
  RUNTIME_FIU_0 : fault_injection_unit
    generic map (
      g_fault_model => RUNTIME,
      g_lfsr_mask   => "0000000000000000")
    port map (
      s_clk_i             => s_clk_i,
      s_reset_n_i         => s_reset_n_i,
      s_data_i            => s_fiu_connector(1),
      s_shift_enable_i    => s_shift_enable_i,
      s_data_o            => s_fiu_connector(0),
      s_lfsr_i            => s_lfsr_i,
      s_injection_start_i => s_injection_start_i,
      s_select_pattern_i  => s_select_pattern_i,
      s_update_i          => s_update_i,
      s_original_i        => s_original_i(0),
      s_modified_o        => s_modified_o(0));

  -- component instantiation
  RUNTIME_FIU_1 : fault_injection_unit
    generic map (
      g_fault_model => RUNTIME,
      g_lfsr_mask   => "0110000000001100")
    port map (
      s_clk_i             => s_clk_i,
      s_reset_n_i         => s_reset_n_i,
      s_data_i            => s_fiu_connector(2),
      s_shift_enable_i    => s_shift_enable_i,
      s_data_o            => s_fiu_connector(1),
      s_lfsr_i            => s_lfsr_i,
      s_injection_start_i => s_injection_start_i,
      s_select_pattern_i  => s_select_pattern_i,
      s_update_i          => s_update_i,
      s_original_i        => s_original_i(1),
      s_modified_o        => s_modified_o(1));

  -- component instantiation
  STUCK_AT_0_FIU : fault_injection_unit
    generic map (
      g_lfsr_mask   => "0000000000000000",
      g_fault_model => STUCK_AT_0)
    port map (
      s_clk_i             => s_clk_i,
      s_reset_n_i         => s_reset_n_i,
      s_data_i            => s_fiu_connector(3),
      s_shift_enable_i    => s_shift_enable_i,
      s_data_o            => s_fiu_connector(2),
      s_lfsr_i            => s_lfsr_i,
      s_injection_start_i => s_injection_start_i,
      s_select_pattern_i  => s_select_pattern_i,
      s_update_i          => s_update_i,
      s_original_i        => s_original_i(2),
      s_modified_o        => s_modified_o(2));

  -- component instantiation
  STUCK_AT_1_FIU : fault_injection_unit
    generic map (
      g_lfsr_mask   => "0000000000000000",
      g_fault_model => STUCK_AT_1)
    port map (
      s_clk_i             => s_clk_i,
      s_reset_n_i         => s_reset_n_i,
      s_data_i            => s_fiu_connector(4),
      s_shift_enable_i    => s_shift_enable_i,
      s_data_o            => s_fiu_connector(3),
      s_lfsr_i            => s_lfsr_i,
      s_injection_start_i => s_injection_start_i,
      s_select_pattern_i  => s_select_pattern_i,
      s_update_i          => s_update_i,
      s_original_i        => s_original_i(3),
      s_modified_o        => s_modified_o(3));


  -- component instantiation
  DELAY_FIU : fault_injection_unit
    generic map (
      g_fault_model => DELAY,
      g_lfsr_mask   => "0110000000001100")
    port map (
      s_clk_i             => s_clk_i,
      s_reset_n_i         => s_reset_n_i,
      s_data_i            => s_fiu_connector(5),
      s_shift_enable_i    => s_shift_enable_i,
      s_data_o            => s_fiu_connector(4),
      s_lfsr_i            => s_lfsr_i,
      s_injection_start_i => s_injection_start_i,
      s_select_pattern_i  => s_select_pattern_i,
      s_update_i          => s_update_i,
      s_original_i        => s_original_i(4),
      s_modified_o        => s_modified_o(4));

  -- component instantiation
  SEU_FIU : fault_injection_unit
    generic map (
      g_fault_model => SEU,
      g_lfsr_mask   => "0110000000001100")
    port map (
      s_clk_i             => s_clk_i,
      s_reset_n_i         => s_reset_n_i,
      s_data_i            => s_fiu_connector(6),
      s_shift_enable_i    => s_shift_enable_i,
      s_data_o            => s_fiu_connector(5),
      s_lfsr_i            => s_lfsr_i,
      s_injection_start_i => s_injection_start_i,
      s_select_pattern_i  => s_select_pattern_i,
      s_update_i          => s_update_i,
      s_original_i        => s_original_i(5),
      s_modified_o        => s_modified_o(5));

  -- component instantiation
  STUCK_OPEN_FIU : fault_injection_unit
    generic map (
      g_lfsr_mask   => "0000001111000000",
      g_fault_model => STUCK_OPEN)
    port map (
      s_clk_i             => s_clk_i,
      s_reset_n_i         => s_reset_n_i,
      s_data_i            => s_fiu_connector(7),
      s_shift_enable_i    => s_shift_enable_i,
      s_data_o            => s_fiu_connector(6),
      s_lfsr_i            => s_lfsr_i,
      s_injection_start_i => s_injection_start_i,
      s_select_pattern_i  => s_select_pattern_i,
      s_update_i          => s_update_i,
      s_original_i        => s_original_i(6),
      s_modified_o        => s_modified_o(6));

  -- component instantiation
  PASS_THROUGH_FIU : fault_injection_unit
    generic map (
      g_lfsr_mask   => "0000000000000000",
      g_fault_model => PASS_THRU)
    port map (
      s_clk_i             => s_clk_i,
      s_reset_n_i         => s_reset_n_i,
      s_data_i            => s_data_bit,
      s_shift_enable_i    => s_shift_enable_i,
      s_data_o            => s_fiu_connector(7),
      s_lfsr_i            => s_lfsr_i,
      s_injection_start_i => s_injection_start_i,
      s_select_pattern_i  => s_select_pattern_i,
      s_update_i          => s_update_i,
      s_original_i        => s_original_i(7),
      s_modified_o        => s_modified_o(7));

  -- clock generation
  s_clk_i     <= not s_clk_i after 10 ns;
  s_reset_n_i <= '0', '1'    after 10 ns;

  -- waveform generation
  WaveGen_Proc : process
  begin
    -- insert signal assignments here
    s_original_i <= (others => '0');
    wait_clock_cycles(s_clk_i, '1', 100);
    s_original_i <= (others => '1');
    wait_clock_cycles(s_clk_i, '1', 100);
  end process WaveGen_Proc;

  p_data : process
    file f_data_in       : text open read_mode is g_data_file_name;
    variable L           : line;
    variable config_data : std_logic_vector(c_number_fius*c_num_select_bits*c_num_patterns-1 downto 0);
    variable good        : boolean;

  begin
    s_select_pattern_i  <= std_logic_vector(to_unsigned(c_num_patterns-1, s_select_pattern_i'length));
    s_data_bit          <= '0';
    s_injection_start_i <= '0';
    s_shift_enable_i    <= '0';
    s_update_i          <= '0';
    wait for g_inter_bit_time;
    l_read_file : while not endfile(f_data_in) loop
      readline(f_data_in, L);
      read(L, config_data, GOOD => good);
      if not good then
        next;
      end if;
      l_shift_fiu : for i in 0 to c_number_fius*c_num_select_bits*c_num_patterns-1 loop
        s_data_bit       <= config_data(i);
        s_shift_enable_i <= '1';
        wait until s_clk_i = '1';
        s_shift_enable_i <= '0';
        wait until s_clk_i = '1';
        wait for g_inter_bit_time;
      end loop;
      s_data_bit <= '0';
      wait for g_inject_time;
      s_update_i <= '1';
      wait until s_clk_i = '1';
      s_update_i <= '0';
      wait until s_clk_i = '1';
      for j in 0 to c_num_patterns-1 loop
        s_select_pattern_i  <= std_logic_vector(to_unsigned(j, s_select_pattern_i'length));
        s_injection_start_i <= '1';
        wait until s_clk_i = '1';
        s_injection_start_i <= '0';
        wait until s_clk_i = '1';
        wait for g_inject_time/c_num_patterns;
      end loop;
    end loop;
    wait;
  end process p_data;

  p_lfsr : process
    variable rand         : real;
    variable seed1, seed2 : positive;
  begin
    seed1 := g_seed1;
    seed2 := g_seed2;
    while true loop
      UNIFORM(seed1, seed2, rand);
      s_lfsr_i <= std_logic_vector(to_unsigned(integer(trunc(rand*(2.0**c_lfsr_width))), c_lfsr_width));
      wait until s_clk_i = '1';
    end loop;
  end process p_lfsr;

end architecture sim;

-------------------------------------------------------------------------------

configuration fault_injection_unit_tb_sim_cfg of fault_injection_unit_tb is
  for sim
  end for;
end fault_injection_unit_tb_sim_cfg;

-------------------------------------------------------------------------------