fault_injection_uart_tb.vhd 6.66 KB
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-- Fault InJection Instrumenter (FIJI)
-- https://embsys.technikum-wien.at/projects/vecs/fiji
--
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-- The creation of this file has been supported by the publicly funded
-- R&D project Josef Ressel Center for Verification of Embedded Computing
-- Systems (VECS) managed by the Christian Doppler Gesellschaft (CDG).
--
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-- Authors:
-- Christian Fibich <fibich@technikum-wien.at>
-- Stefan Tauner <tauner@technikum-wien.at>
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--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable
-- law or agreed to in writing, software, hardware and materials
-- distributed under this License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either expressed or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- See the LICENSE file for more details.
--
-- Description:
--  Fault injection UART receiver testbench file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;

library work;
use work.fault_injection_uart_pkg.all;

-------------------------------------------------------------------------------

entity fault_injection_uart_tb is
  generic (
    g_baudrate          : natural;
    g_clock_frequency   : natural;
    g_rx_data_file_name : string;
    g_tx_data_file_name : string);

end entity fault_injection_uart_tb;


architecture sim of fault_injection_uart_tb is

  -- serial MARK level  (Stop Bit)
  constant c_rs232_mark  : std_logic := '1';
  -- serial SPACE level (Start Bit)
  constant c_rs232_space : std_logic := '0';


  -- component ports
  signal s_clk_i        : std_logic := '1';
  signal s_reset_n_i    : std_logic;
  signal s_rx_i         : std_logic;
  signal s_rx           : std_logic;
  signal s_sel          : std_logic := '0';
  signal s_data_o       : std_logic;
  signal s_data_valid_o : std_logic;
  signal s_byte_start_o : std_logic;
  signal s_tx_o         : std_logic;
  signal s_tx_ready_o   : std_logic;    -- transmitter ready out
  signal s_tx_data_i    : std_logic_vector(6 downto 0);  -- 7 bit data
  signal s_tx_enable_i  : std_logic;    -- transmitter enable

  -----------------------------------------------------------------------------
  -- Procedure from UART2BUS testbench
  -----------------------------------------------------------------------------

  procedure serial_byte(
    constant C_RS232_MARK  : in  std_logic;
    constant C_RS232_SPACE : in  std_logic;
    constant C_BAUD_RATE   : in  natural;
    constant C_BAUD_ERROR  : in  natural;
    variable data          : in  string(10 downto 1);
    signal uart_rx         : out std_logic) is
  begin
    l_serial_byte : for i in 1 to 10 loop
      case data(i) is
        when 'M' =>
          uart_rx <= C_RS232_MARK;
        when 'S' =>
          uart_rx <= C_RS232_SPACE;
        when '1' =>
          uart_rx <= C_RS232_MARK;
        when '0' =>
          uart_rx <= C_RS232_SPACE;
        when 'X' =>
          uart_rx <= C_RS232_SPACE;
          wait for 200 ms / (C_BAUD_RATE - C_BAUD_ERROR);
          uart_rx <= C_RS232_MARK;
          wait for 800 ms / (C_BAUD_RATE - C_BAUD_ERROR);
          next;
        when others =>
          uart_rx <= not(C_RS232_SPACE);
      end case;
      report "Bit: "&integer'image(i)&": "&data(i);
      wait for 1000 ms / (C_BAUD_RATE - C_BAUD_ERROR);
    end loop;
    uart_rx <= not(C_RS232_SPACE);
  end procedure;

begin  -- architecture sim

  fault_injection_uart_1 : fault_injection_uart
    generic map (
      g_baudrate        => g_baudrate,
      g_clock_frequency => g_clock_frequency)
    port map (
      s_clk_i        => s_clk_i,
      s_reset_n_i    => s_reset_n_i,
      s_rx_i         => s_rx_i,
      s_tx_o         => s_tx_o,
      s_tx_ready_o   => s_tx_ready_o,
      s_tx_data_i    => s_tx_data_i,
      s_tx_enable_i  => s_tx_enable_i,
      s_data_o       => s_data_o,
      s_data_valid_o => s_data_valid_o,
      s_byte_start_o => s_byte_start_o);


  -- clock generation
  s_clk_i     <= not s_clk_i after (1 sec)/(2*g_clock_frequency);
  s_reset_n_i <= '0', '1'    after (1 sec)/(2*g_clock_frequency);

  s_rx_i <= s_rx when s_sel = '0' else s_tx_o;

  -- waveform generation
  WaveGen_Proc : process
    file f_data_in_1 : text open read_mode is g_rx_data_file_name;
    file f_data_in_2 : text open read_mode is g_tx_data_file_name;
    variable L       : line;
    variable data    : string(10 downto 1);
    variable txdta   : std_logic_vector(6 downto 0);
    variable good    : boolean;
  begin
    s_tx_enable_i <= '0';
    s_tx_data_i   <= (others => '0');
    -- insert signal assignments here
    s_rx          <= not (c_rs232_space);
    wait for 10000 ms / g_baudrate;
    l_read_file_1 : while not endfile(f_data_in_1) loop
      readline(f_data_in_1, L);
      read(L, data, GOOD => good);
      if not good then
        next;
      elsif data(10) = '#' then
        next;
      end if;
      report "read byte: "&data;

      serial_byte(c_rs232_mark, c_rs232_space, g_baudrate, 0, data, s_rx);
      -- pause 8 bit times
      wait for 8000 ms / g_baudrate;
    end loop;
    s_sel <= '1';
    l_read_file_2 : while not endfile(f_data_in_2) loop
      readline(f_data_in_2, L);
      read(L, txdta, GOOD => good);
      if not good then
        next;
      end if;
      s_tx_enable_i <= '1';
      s_tx_data_i   <= txdta;
      wait until s_clk_i = '1';
      s_tx_enable_i <= '0';
      wait until s_tx_ready_o = '1';
    end loop;
    wait;
  end process WaveGen_Proc;

  rec_proc : process
    variable v_tx : std_logic;
  begin
    wait until s_tx_o'event and s_tx_o = c_rs232_space;
    wait for 500 ms / g_baudrate;
    l_receive : for byte in 0 to 7 loop
      wait for 1000 ms / g_baudrate;
      if s_tx_o = c_rs232_space then
        v_tx := '0';
      else
        v_tx := '1';
      end if;
      if byte = 7 then
        report "[TB:rec_proc] Received parity bit = "&std_logic'image(v_tx);
      else
        report "[TB:rec_proc] Received data bit "&integer'image(byte)&" = "&std_logic'image(v_tx);
      end if;
    end loop;
    wait for 1000 ms / g_baudrate;
    if s_tx_o = c_rs232_space then
      v_tx := '0';
    else
      v_tx := '1';
    end if;
    report "[TB:rec_proc] Stop bit = "&std_logic'image(v_tx);
  end process rec_proc;


end architecture sim;

-------------------------------------------------------------------------------