fault_injection_tx_buffer_tb.vhd 4.61 KB
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-- Fault InJection Instrumenter (FIJI)
-- https://embsys.technikum-wien.at/projects/vecs/fiji
--
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-- The creation of this file has been supported by the publicly funded
-- R&D project Josef Ressel Center for Verification of Embedded Computing
-- Systems (VECS) managed by the Christian Doppler Gesellschaft (CDG).
--
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-- Authors:
-- Christian Fibich <fibich@technikum-wien.at>
-- Stefan Tauner <tauner@technikum-wien.at>
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--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable
-- law or agreed to in writing, software, hardware and materials
-- distributed under this License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either expressed or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- See the LICENSE file for more details.
--
-- Description:
--  Fault injection transmit buffer testbench file
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--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-------------------------------------------------------------------------------

entity fault_injection_tx_buffer_tb is

end entity fault_injection_tx_buffer_tb;

-------------------------------------------------------------------------------

architecture sim of fault_injection_tx_buffer_tb is

  -- component generics
  constant g_buffer_width : natural range 1 to 128 := 7;
  constant g_buffer_depth : natural range 0 to 128 := 16;

  -- component ports
  signal s_reset_n_i : std_logic;
  signal s_data_i    : std_logic_vector(6 downto 0);
  signal s_data_o    : std_logic_vector(6 downto 0);
  signal s_rdrq_i    : std_logic;
  signal s_wrrq_i    : std_logic;
  signal s_empty_o   : std_logic;
  signal s_full_o    : std_logic;

  -- clock
  signal s_clk_i : std_logic := '1';

begin  -- architecture sim

  -- component instantiation
  DUT : entity work.fault_injection_tx_buffer
    generic map (
      g_buffer_width => g_buffer_width,
      g_buffer_depth => g_buffer_depth)
    port map (
      s_clk_i     => s_clk_i,
      s_reset_n_i => s_reset_n_i,
      s_data_i    => s_data_i,
      s_data_o    => s_data_o,
      s_rdrq_i    => s_rdrq_i,
      s_wrrq_i    => s_wrrq_i,
      s_empty_o   => s_empty_o,
      s_full_o    => s_full_o);

  -- clock generation
  s_clk_i     <= not s_clk_i after 10 ns;
  s_reset_n_i <= '0', '1'    after 10 ns;

  -- waveform generation
  WaveGen_Proc : process
  begin
    -- insert signal assignments here
    s_data_i <= (others => '0');
    s_rdrq_i <= '0';
    s_wrrq_i <= '0';

    l_wait_until_write_1 : for i in 0 to 5 loop
      wait until s_clk_i = '1';
    end loop;

    s_wrrq_i <= '1';

    l_write_data_1 : for i in 0 to 20 loop
      s_data_i <= std_logic_vector(to_unsigned(i, 7));
      wait until s_clk_i = '1';
    end loop;

    s_wrrq_i <= '0';

    l_wait_until_read_1 : for i in 0 to 5 loop
      wait until s_clk_i = '1';
    end loop;

    s_rdrq_i <= '1';

    l_read_data_1 : for i in 0 to 20 loop
      wait until s_clk_i = '1';
    end loop;

    s_rdrq_i <= '0';

    l_wait_until_write_2 : for i in 0 to 5 loop
      wait until s_clk_i = '1';
    end loop;

    s_wrrq_i <= '1';

    l_write_data_2 : for i in 0 to 4 loop
      s_data_i <= std_logic_vector(to_unsigned(15-i, 7));
      wait until s_clk_i = '1';
    end loop;

    s_wrrq_i <= '0';
    s_rdrq_i <= '1';

    l_read_data_2 : for i in 0 to 2 loop
      wait until s_clk_i = '1';
    end loop;

    s_rdrq_i <= '0';
    s_wrrq_i <= '1';

    l_write_data_3 : for i in 0 to 4 loop
      s_data_i <= std_logic_vector(to_unsigned(15-i, 7));
      wait until s_clk_i = '1';
    end loop;

    s_wrrq_i <= '0';
    s_rdrq_i <= '1';

    l_read_data_3 : for i in 0 to 10 loop
      wait until s_clk_i = '1';
    end loop;

    s_rdrq_i <= '1';
    s_wrrq_i <= '1';

    s_data_i <= std_logic_vector(to_unsigned(127, 7));

    wait until s_clk_i = '1';

    s_rdrq_i <= '1';
    s_wrrq_i <= '0';

    wait until s_clk_i = '1';

    wait;

  end process WaveGen_Proc;



end architecture sim;

-------------------------------------------------------------------------------

configuration fault_injection_tx_buffer_tb_sim_cfg of fault_injection_tx_buffer_tb is
  for sim
  end for;
end fault_injection_tx_buffer_tb_sim_cfg;

-------------------------------------------------------------------------------