SystemVerilog.pm 10.8 KB
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#-----------------------------------------------------------------------
# Fault InJection Instrumenter (FIJI)
# https://embsys.technikum-wien.at/projects/vecs/fiji
#
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# The creation of this file has been supported by the publicly funded
# R&D project Josef Ressel Center for Verification of Embedded Computing
# Systems (VECS) managed by the Christian Doppler Gesellschaft (CDG).
#
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# Authors:
# Christian Fibich <fibich@technikum-wien.at>
# Stefan Tauner <tauner@technikum-wien.at>
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#
# This module is free software; you can redistribute it and/or modify
# it under the same terms as Perl itself.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
#
# See the LICENSE file for more details.
#-----------------------------------------------------------------------

## @file SystemVerilog.pm
# @brief Contains class \ref FIJI::Tests::SystemVerilog

## @class FIJI::Tests::SystemVerilog
# @brief Used to export SystemVerilog files for reproducing faults in simulations

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package FIJI::Tests::SystemVerilog;
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use strict;
use warnings;
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use FIJI qw(:all);
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use POSIX qw(ceil);
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sub period_si {
    my $num = shift;
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    my %map = (
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     10**0  => "sec",
     10**3  => "ms",
     10**6  => "us",
     10**9  => "ns",
    10**12  => "ps",
    10**15  => "fs");
    my $idx;
    my @sorted_keys = sort (keys %map);
    for ($idx = 0; $idx < @sorted_keys; $idx++) {
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        last if $sorted_keys[$idx] > $num;
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    }
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    my $mul = $sorted_keys[$idx-1]/$num;
    my $si  = $map{$sorted_keys[$idx-1]};
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    return ($mul, $si);

}

sub export_timing {
    my ($timer,$settings_ref,$reset,$trigger,$underrun) = @_;

    my $indent = "        ";

    my $vlog;

    my ($period,$si) = period_si($settings_ref->{'design'}->{'FREQUENCY'});


    if (defined $underrun && $underrun < 0 && $trigger eq 'NONE') {
        # no need to calculate/wait for underrun when there is an external trigger (?)
        $vlog .= $indent."// BEGIN underrun time ($underrun)\n";
        $vlog .= $indent."#".(-1*$underrun*$period)."$si;\n";
    }

    if (defined $trigger && $trigger ne 'NONE') {
        $vlog .= $indent."wait until ";
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        my $n = $trigger;
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        $n =~ s/EXT/EXT_IN/;
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        my $edge = ($settings_ref->{'design'}->{"TRIG_${trigger}_ACT"} == 0) ? "neg" : "pos";
        $vlog .= '@('.$edge.'edge '.$settings_ref->{'design'}->{'TRIG_'.$n.'_NAME'}.');\n';
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        $vlog .= $indent."#".(2*$period)."$si; // trigger synchronization/edge detection\n";
    }

    if (defined $reset && $reset != 0) {
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        $vlog .= $indent."// BEGIN reset time ($settings_ref->{'design'}->{'RST_DUT_IN_DUR'})\n";
        $vlog .= $indent."#".(($settings_ref->{'design'}->{'RST_DUT_IN_DUR'})*$period)."$si;\n";
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    }

    $vlog .= $indent."// BEGIN timer time ($timer)\n";
    $vlog .= $indent."#".(($timer)*$period)."$si;";

    return $vlog;
}

sub export_fiu {
    my ($fiu_idx, $global_settings_ref) = @_;

    my $design_ref = $global_settings_ref->{'design'};

    my ($period,$si) = period_si($global_settings_ref->{'design'}->{'FREQUENCY'});
    my $dpath = (@{$global_settings_ref->{'fius'}}[$fiu_idx])->{'FIU_DRIVER_PATH'};
    my $pfx  =  "FIU_${fiu_idx}";
    my $vlog =<<"END_VLOG";
//----------------------------------------------------------------------
// BEGIN ${pfx}
//----------------------------------------------------------------------

// BEGIN declaration code

    wire ${pfx}_stuck_at_0;
    wire ${pfx}_stuck_at_1;
    wire ${pfx}_not;
    reg  ${pfx}_delayed;
    wire ${pfx}_random;
    reg  [2:0] ${pfx}_select;
    wire ${dpath}_original;
// END declaration code
// BEGIN stimulus code

    assign ${pfx}_stuck_at_0 = 1'b0;
    assign ${pfx}_stuck_at_1 = 1'b1;
    assign ${pfx}_not        = ~${dpath}_original;
    
    initial
    begin
        ${pfx}_delayed <= 0;
    end

    always \@(posedge (clk))
        ${pfx}_delayed <= ${dpath};

    assign ${dpath} = (${pfx}_select == 1) ? ${pfx}_stuck_at_0 :
                      (${pfx}_select == 2) ? ${pfx}_stuck_at_1 :
                      (${pfx}_select == 3) ? ${pfx}_delayed    :
                      (${pfx}_select == 4) ? ${pfx}_not        :
                      (${pfx}_select == 5) ? ${pfx}_random     :
                         ${dpath}_original;

// END stimulus code

//----------------------------------------------------------------------
// END ${pfx}
//----------------------------------------------------------------------


END_VLOG

    return $vlog;
}

sub export_controller {

    my ($tests, $final_test, $num_repetitions, $global_settings_ref) = @_;

    my ($period,$si) = period_si($global_settings_ref->{'design'}->{'FREQUENCY'});
    my $design_ref = $global_settings_ref->{'design'};
    my $cfg_bits   = $design_ref->{'CFGS_PER_MSG'} * $design_ref->{'FIU_NUM'} * $design_ref->{'FIU_CFG_BITS'};
    my $timer_bits = $design_ref->{'CFGS_PER_MSG'} * $design_ref->{'TIMER_WIDTH'} * 8;
    my $proto_bits = 16 + #ID
                     8 +  #cfg word
                     8;   #crc
    my $raw_bits   = (10/8) * ( $cfg_bits+$timer_bits+$proto_bits);
    my $config_duration = POSIX::ceil(($raw_bits/$design_ref->{'BAUDRATE'})*$design_ref->{'FREQUENCY'});
    my $lfsr = $design_ref->{'LFSR_WIDTH'}-1;
    my $vlog=<<"END_HDR";
//----------------------------------------------------------------------
// BEGIN VLOG Fault Controller
//----------------------------------------------------------------------

// BEGIN Declarations

    `define c_lfsr_width $design_ref->{'LFSR_WIDTH'}
    `define c_lfsr_seed $design_ref->{'LFSR_SEED'}
    `define c_lfsr_poly $design_ref->{'LFSR_POLY'}

    wire s_reset;
    reg  [$lfsr:0] s_lfsr;
    wire s_clk;
// END Declarations


    assign s_clk = add.some.hierarchy.here.$global_settings_ref->{'design'}->{'CLOCK_NET'};


// BEGIN LFSR

    always @(posedge s_clk or posedge s_reset)
    begin
        if (s_reset)
            s_lfsr <= `c_lfsr_seed;
        else
            begin
                if (s_lfsr[`c_lfsr_width-1] == 1'b1)     // if leftmost bit is '1'
                    begin
                        // XOR content with poly & shift left
                        s_lfsr[`c_lfsr_width-1:0] <= {s_lfsr[`c_lfsr_width-2:0],1'b0} ^ `c_lfsr_poly;
                    end
                else
                    begin
                        // just shift left
                        s_lfsr[`c_lfsr_width-1:0] <= {s_lfsr[`c_lfsr_width-2:0],1'b0};
                    end
            end
    end

// END LFSR

// BEGIN assign LFSR_output
END_HDR

    for (my $fi = 0; $fi < $global_settings_ref->{'design'}->{'FIU_NUM'} ; $fi++) {
        my $fiu = @{$global_settings_ref->{'fius'}}[$fi];
        $vlog .= "    assign add.some.hierarchy.here.FIU_${fi}_random = ";
        $vlog .= " | (s_lfsr & $design_ref->{'LFSR_WIDTH'}'d$fiu->{'FIU_LFSR_MASK'});\n";
    }

$vlog .=<<"END_HDR";
// END assign LFSR_output

// BEGIN assign reset
END_HDR

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    my @conditions;
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    push @conditions, "(.add.some.hierarchy.here.$global_settings_ref->{'design'}->{'RST_EXT_IN_NAME'} = 1'b$global_settings_ref->{'design'}->{'RST_EXT_ACT'})" if $global_settings_ref->{'design'}->{'RST_EXT_EN'};
    push @conditions, "(.add.some.hierarchy.here.$global_settings_ref->{'design'}->{'RST_DUT_OUT_NAME'} = 1'b$global_settings_ref->{'design'}->{'RST_DUT_OUT_ACT'})" if $global_settings_ref->{'design'}->{'RST_DUT_OUT_EN'};
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    $vlog .= "        assign s_reset = (".join(" or ",@conditions).");";

$vlog .=<<"END_HDR";
//  END assign reset

// BEGIN Sequencer
    initial
    begin
END_HDR
    for (my $fi = 0; $fi < $global_settings_ref->{'design'}->{'FIU_NUM'} ; $fi++) {
        $vlog .= "        add.some.hierarchy.here.FIU_${fi}_select <= 3'd0; // NONE\n";
    }

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    if ($global_settings_ref->{'design'}->{'RST_EXT_EN'} || $global_settings_ref->{'design'}->{'RST_DUT_OUT_EN'}) {
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        $vlog .= "        @(negedge s_reset);\n";
        $vlog .= "        @(posedge s_clk); // synchronize with clock\n"; 
    }
    my @fault_vlog;
    my $time = localtime;
    my $tv = 0;
    for (my $rep = 0; $rep < $num_repetitions; $rep++) {
        push @fault_vlog, "        // BEGIN Repetition $rep";
        for (my $ti = 0 ; $ti < @{$tests->{'tests'}} ; $ti++) {
            last if ($rep == $num_repetitions - 1 && $ti > $final_test);
            
            push @fault_vlog, "        // BEGIN Test $ti";
            push @fault_vlog, "        \$display(\"[FIJI] BEGIN Test $ti\");";
            my $test   = @{$tests->{'tests'}}[$ti];
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            my $rst    = ($test->{"RST_DUT_AFTER_CFG"}) ? "true" : "false";
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            my $trig   = ($test->{"TRIGGER"});
            
            # calculate how long it takes after finishing the previous
            # fault to load the next configuration, assuming we have
            # immediately started after we got a READY message
            my $underrun = $tv - $config_duration;
            for (my $ci = 1 ; $ci <= $global_settings_ref->{'design'}->{'CFGS_PER_MSG'} ; $ci++) {
                push @fault_vlog, "        // BEGIN Fault $ci";
                push @fault_vlog, "        \$display(\"[FIJI] BEGIN fault $ci\");";
                push @fault_vlog, "        \$display(\"[FIJI] Timer value ".$test->{"TIMER_VALUE_$ci"}."\");";
                if ($ci == 1) {
                    push @fault_vlog, export_timing($test->{"TIMER_VALUE_$ci"},$global_settings_ref,$rst,$trig,$underrun);
                } else {
                    push @fault_vlog, export_timing($test->{"TIMER_VALUE_$ci"},$global_settings_ref);
                }
                push @fault_vlog, "         @(posedge s_clk); // synchronize with clock\n"; 
                my @disable_list;
                for (my $fi = 0; $fi < $global_settings_ref->{'design'}->{'FIU_NUM'} ; $fi++) {
                    my $fault  = $test->{"FIU_${fi}_FAULT_${ci}"};
                    push @fault_vlog, "        \$display(\"[FIJI] FIU $fi: $fault\");";
                    my $signal = "add.some.hierarchy.here.FIU_${fi}_select";
                    push @fault_vlog, "        ${signal} <= 3'd".(FIUENUM->{$fault})."; // $fault";
                    push @disable_list, $signal if ($fault eq "SEU");
                }
                push @fault_vlog, "        #$period$si " if (@disable_list > 0);
                for my $disable_signal (@disable_list) {
                    push @fault_vlog, "        ${disable_signal} <= ".(FIUENUM->{'NONE'})."; // NONE";
                }
                $tv = $test->{"TIMER_VALUE_$ci"};
            }
            push @fault_vlog, "        // END Test $ti\n";
        }
        push @fault_vlog, "        // END Repetition $rep\n";
    }
    $vlog .= join("\n", @fault_vlog);

    $vlog .=<<"END_VLOG_FOOTER";
        \$display("[FIJI] Test ended.");
    end;
// END Sequencer

//----------------------------------------------------------------------
// END VLOG Fault Controller
//----------------------------------------------------------------------


END_VLOG_FOOTER

    return $vlog;

}

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