08-demo.tex 14.8 KB
 Stefan Tauner committed May 04, 2018 1 2 3 4 5 6 \section{Demo: TMR VGA} \subsection{Use Case} The \ac{TMR} \ac{VGA} demo design is intended to demonstrate the effects of fault injection in an TMR A sprite engine draws a sprite of a small airplane on the screen in front  Christian Fibich committed May 04, 2018 7 of a blue-red gradient background. The sprite of the airplane is moved across the  Stefan Tauner committed May 04, 2018 8 screen in successive frames, changing direction when it reaches any of  Stefan Tauner committed May 04, 2018 9 the visible screen borders. Screenshots can be seen in \Cref{fig:tmrvga_screenshot}.  Christian Fibich committed May 04, 2018 10 11 12 13 14 15 The left side shows the error-free case, a stuck-open error in the sprite engine can be seen on the right side. \begin{figure}[htb] \centering \includegraphics[width=0.8\linewidth]{img/tmrvga_screenshot.jpg}  Stefan Tauner committed May 04, 2018 16 \caption{\ac{TMR} \ac{VGA} Screenshots}  Christian Fibich committed May 04, 2018 17 18 \label{fig:tmrvga_screenshot} \end{figure}  Stefan Tauner committed May 04, 2018 19 20  The use case is designated for use with the Cyclone III-based DE0 development  Stefan Tauner committed May 04, 2018 21 22 23 board from Terasic\footnote{\url{http://de0.terasic.com.tw}, visited on August~29, 2016}, the Artix~7-based Basys~3\footnote{\url{https://reference.digilentinc.com/reference/programmable-logic/basys-3/start}, visited on April~12, 2017}, or the Zynq~7000-based Zybo\footnote{\url{https://reference.digilentinc.com/reference/programmable-logic/zybo/start}, visited on April~12, 2017},  Stefan Tauner committed May 04, 2018 24 25 26 27 28 29 30 31 32 33 34 35 36 37 but is portable to other boards providing a \ac{VGA} connector with little effort. \begin{figure}[htb] \centering \input{img/blockdiagram-usecase.tex} \caption{\ac{TMR} \ac{VGA} Use Case} \label{fig:tmrvga} \end{figure} The design contains a \ac{VGA} timing generator module, which provides HSync and VSync signals as well as the row and column in the current frame. The output of the sprite engine is the color of the current pixel, blanked in the non-visible area of the \ac{VGA} timing. This sprite engine is triplicated, as an analogy to triplicated avionics in an actual airplane. Majority voting is performed over the three color channels before outputting the color value to a parallel \ac{DAC}.  Christian Fibich committed May 04, 2018 38 The voters are also able to determine if a 2:1 mismatch has occurred.  Stefan Tauner committed May 04, 2018 39 40 41 42 43 44 45 46 A coarse block diagram of the design can be seen in \Cref{fig:tmrvga}. An important thing to note is that the sprite position registers within the sprite engines are not converged using majority voting. Thus, faults affecting the direction register will cause the domain 0 to permanently diverge from the others until the design is reset. In a real-world design the states of the redundant units would usually be determined by the voter. \subsection{Hardware Setup}  Stefan Tauner committed May 04, 2018 47 \subsubsection{Digilent Basys 3}  Stefan Tauner committed May 04, 2018 48 \begin{itemize}  Stefan Tauner committed May 04, 2018 49 50 51 52 53 54  \item Connect the host with the micro USB port (PROG). This will not only allow programming the FPGA but also transport the UART packets for the run-time communication. \item Connect a VGA-compatible monitor to the VGA port. The design generates a 640x480 @ 25Mhz VGA signal. \item The dip-switch SW0 controls if TMR is enabled (towards the board edge is off). \item BTNC resets the design when pressed.  Christian Fibich committed May 04, 2018 55  \item The external trigger is activated when BTNU is pressed.  Stefan Tauner committed May 04, 2018 56  \item The four rightmost LEDs above the dip switches (LD0-LD3) show the error detection state:  Stefan Tauner committed May 04, 2018 57  \begin{itemize}  Stefan Tauner committed May 04, 2018 58 59 60 61 62 63 64 65 66 67 68 69 70 71  \item LD0 shows if any error has been detected. \item LD1-3 show which voter (Red, Green, Blue) detected the error. \end{itemize} \end{itemize} \subsubsection{Digilent Zybo} \begin{itemize} \item Connect a 3V3 Serial TTL cable to the Zybo: \begin{itemize} \item Connect \textit{Ground} to PMOD JE5. \item Connect \textit{TXD (Host-to-Device)} to PMOD JE1. \item Connect \textit{RXD (Device-to-Host)} to PMOD JE2. \item Leave \textit{\#RTS} unconnected. \item Connect \textit{\#CTS} to GND (or leave unconnected if your cable pulls it down).  Stefan Tauner committed May 04, 2018 72  \item If your cable requires an I/O voltage input (e.g., FTDI TTL-232R-VIP),  Stefan Tauner committed May 04, 2018 73  connect the correspondig wire to PMOD JE6.  Stefan Tauner committed May 04, 2018 74  \end{itemize}  Stefan Tauner committed May 04, 2018 75 76  \item Connect a VGA-compatible monitor to the VGA port. The design generates a 640x480 @ 25Mhz VGA signal.  Christian Fibich committed May 04, 2018 77  \item The dip-switch SW0 controls if TMR is enabled.  Stefan Tauner committed May 04, 2018 78  \item BTN0 resets the design when pressed.  Christian Fibich committed May 04, 2018 79  % FIXME: External Trigger  Stefan Tauner committed May 04, 2018 80  \item The LEDs above the dip switches (LD0-LD3) show the error detection state:  Christian Fibich committed May 04, 2018 81  \begin{itemize}  Stefan Tauner committed May 04, 2018 82 83  \item LD0 shows if any error has been detected. \item LD1-3 show which voter (Red, Green, Blue) detected the error.  Christian Fibich committed May 04, 2018 84  \end{itemize}  Stefan Tauner committed May 04, 2018 85 86 \end{itemize}  Stefan Tauner committed May 04, 2018 87 \subsubsection{Terasic DE0}  Christian Fibich committed May 04, 2018 88   Stefan Tauner committed May 04, 2018 89 \begin{itemize}  Stefan Tauner committed May 04, 2018 90  \item Connect a 3V3 Serial TTL cable to the DE0:  Christian Fibich committed May 04, 2018 91 92 93 94  \begin{minipage}[h]{\linewidth} \centering \begin{minipage}{0.45\linewidth}  Stefan Tauner committed May 04, 2018 95  \begin{itemize}  Stefan Tauner committed May 04, 2018 96 97 98 99 100  \item Connect \textit{Ground} to any GND pin on GPIO1 (e.g., J5.30). \item Connect \textit{TXD (Host-to-Device)} to GPIO1\_D31 (J5.40). \item Connect \textit{RXD (Device-to-Host)} to GPIO1\_D30 (J5.39). \item Leave \textit{\#RTS} unconnected. \item Connect \textit{\#CTS} to GND (or leave unconnected if your cable pulls it down).  Stefan Tauner committed May 04, 2018 101  \item If your cable requires an I/O voltage input (e.g., FTDI TTL-232R-VIP),  Stefan Tauner committed May 04, 2018 102  connect the correspondig wire to any 3V3 pin on GPIO1 (e.g., J5.29).  Stefan Tauner committed May 04, 2018 103  \end{itemize}  Christian Fibich committed May 04, 2018 104 105 106 107 108 109 110 111 112 113 114 115 116 117  \end{minipage} \hspace{0.05\linewidth} \begin{minipage}{0.45\linewidth} \begin{figure}[H] \centering \includegraphics[height=20em]{img/de0_j5.pdf} \caption{DE0 Connections} \label{fig:de0_connections} \end{figure} \end{minipage} \end{minipage} \vspace{1em}  Christian Fibich committed May 04, 2018 118  \item Connect a VGA-compatible monitor to the VGA port.  Stefan Tauner committed May 04, 2018 119 120 121  The design generates a 640x480 @ 25Mhz VGA signal. \item The dip-switch SW0 controls if TMR is enabled (towards the board edge is off). \item BUTTON0 resets the design.  Christian Fibich committed May 04, 2018 122  \item The external trigger is activated when BUTTON1 is pressed.  Stefan Tauner committed May 04, 2018 123  \item The green LEDs above the three buttons (LEDG0-LEDG3) show the error detection state:  Christian Fibich committed May 04, 2018 124  \begin{itemize}  Stefan Tauner committed May 04, 2018 125 126  \item LEDG0 shows if any error has been detected. \item LEDG1-3 show which voter (Red, Green, Blue) detected the error.  Christian Fibich committed May 04, 2018 127  \end{itemize}  Stefan Tauner committed May 04, 2018 128 129 130 131 \end{itemize} \subsection{Work Flow}  Stefan Tauner committed May 04, 2018 132 133 134 135 136 137 138 139 140 141 142 143 144 145 Due to the various supported boards there are some important points to consider when following the steps: \begin{itemize} \item All paths hereinafter are relative to \texttt{/docs/demos/tmr\_vga}. \item Parts of them are also \textbf{board-specific} and targeting the DE0. They have to be changed for any other board accordingly (\texttt{de0} \textrightarrow{} \texttt{basys3}, \texttt{zybo} etc). \item Depending on the FPGA vendor there are some important differences. Most of them are written out explicitly in the P\&R description to distinguish between Altera Quartus and Xilinx Vivado. Another thing that needs to be changed throughout this tutorial if you are using a Xilinx-based board is the file name suffix of netlists: Instead of \texttt{.vqm} used by Altera you need to use \texttt{.vm} for Xilinx. \end{itemize} To reconstruct the execution of the flow to configure, instrument and synthesize the design with injection logic, the following steps have to be executed. \subsubsection{Input Netlist}  Stefan Tauner committed May 04, 2018 146   Stefan Tauner committed May 04, 2018 147 148 149 150 The steps hereinafter assume that you have already synthesized a netlist of the original design with Synopsis Synplify. A suitable Synopsis project and constraint file is provided in \texttt{synp/de0/}. Synthesizing this with Synplify creates a netlist compatible to our tool (or more specifically to Verilog-Perl). The resulting file should be located in the \texttt{synp} directory (e.g., synp/de0/de0/spriteflyer\_top.vqm).  Stefan Tauner committed May 04, 2018 151 152  \subsubsection{Run setup}  Stefan Tauner committed May 04, 2018 153 154  A pre-configured settings file for \ac{FIJI} is located in \texttt{fiji/de0\_test\_1/fiji/fiji.cfg}. To review the configuration you can open it up in the \ac{FIJI} Setup GUI:  Stefan Tauner committed May 04, 2018 155 156 157 158 159 160  \begin{lstlisting}[style=shell,gobble=8] $perl ../../../bin/fiji_setup.pl -s fiji/de0_test_1/fiji/fiji.cfg \ -n synp/de0/de0/spriteflyer_top.vqm \end{lstlisting} \subsubsection{Instrumentation}  Stefan Tauner committed May 04, 2018 161  To apply the configuration and instrument the design run:  Stefan Tauner committed May 04, 2018 162 163 164 165 166 167  \begin{lstlisting}[style=shell,gobble=8]$ perl ../../../bin/fiji_instrument.pl -s fiji/de0_test_1/fiji/fiji.cfg \ -n synp/de0/de0/spriteflyer_top.vqm \ -o fiji/de0_test_1/fiji \ -p tmr_vga_demo \end{lstlisting}  Stefan Tauner committed May 04, 2018 168   Stefan Tauner committed May 04, 2018 169 170 171 172 173 \subsubsection{Synthesis using Synplify Pro} \begin{enumerate} \item Create a new Synplify project file named 'spriteflyer\_top.prj' in \texttt{fiji/de0\_test\_1/synp} \item Open the project  Stefan Tauner committed May 04, 2018 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189  \item Rename the (default) implementation to \texttt{basys3}, \texttt{de0}, \texttt{zybo}, etc. respectively. Then configure it with the following settings. \medskip Depending on the FPGA vendor you have to select the P\&R tool (in the Implementation Results'' tab): \begin{itemize} \item \textbf{Altera} select Quartus II (Version 13.0) as P\&R Tool \item \textbf{Xilinx} tick Use Vivado~[\ldots]'' then select \texttt{.vm} as Result Format''. \end{itemize} \medskip \textbf{Common for all boards}: \begin{itemize} \item Implementation Results'' tab: Name of the output file containing the Verilog netlist: \texttt{spriteflyer\_top.v(q)m} \item VHDL'' tab: Top Level Entity'': \texttt{fiji\_top} \end{itemize}  Stefan Tauner committed May 04, 2018 190   Stefan Tauner committed May 04, 2018 191 192 193 194 195 196 197  \medskip Finally, you have also to set the correct device in the first tab: \begin{itemize} \item \textbf{Basys~3}: Artix7 XC7A35T-CPG236-1 \item \textbf{DE0}: Cyclone III EP3C16-F484-C6 \item \textbf{Zybo}: Zynq XC7Z010-CLG400-1 \end{itemize}  Stefan Tauner committed May 04, 2018 198   Stefan Tauner committed May 04, 2018 199  \item Add the following files to the project:  Stefan Tauner committed May 04, 2018 200 201 202 203 204 205 206 207  \begin{plainlisting}[gobble=12] fiji/de0_test_1/fiji/tmr_vga_demo_instrumented.vqm fiji/de0_test_1/fiji/tmr_vga_demo_config_pkg.vhd fiji/de0_test_1/fiji/tmr_vga_demo_wrapper.vhd fiji/de0_test_1/fiji/tmr_vga_demo_constraints.synplify.fdc fiji/de0_test_1/synp/spriteflyer_top.fdc /hw/rtl/*.vhd \end{plainlisting}  Stefan Tauner committed May 04, 2018 208 209  The constraints have already been entered for this demo in the \texttt{.fdc} files above. In a real'' flow, they have to be manually transferred from the original Synplify project.  Stefan Tauner committed May 04, 2018 210   Stefan Tauner committed May 04, 2018 211  \item Synthesize (\keystroke{F8})  Stefan Tauner committed May 04, 2018 212 \end{enumerate}  Stefan Tauner committed May 04, 2018 213 214 215 216  \subsubsection{Place-and-Route for Altera FPGAs} To create the final bitstream for Altera FPGAs the instrumented netlist needs to be placed and routed with Quartus~II as follows.  Stefan Tauner committed May 04, 2018 217 218 219 220 221 222 223 224  \begin{enumerate} \item Copy the following files into the \texttt{fiji/de0\_test\_1/quartus} directory: \begin{plainlisting}[gobble=12] synp/de0/de0/spriteflyer_top_p_sprite_rom_s_sprit.hex synp/de0/de0/spriteflyer_top_p_sprite_rom_s_spritmif1.hex synp/de0/de0/spriteflyer_top_p_sprite_rom_s_spritmif2.hex \end{plainlisting}  Stefan Tauner committed May 04, 2018 225 226  \item Create a new project (e.g., \texttt{fiji\_de0.qpf} in \texttt{fiji/de0\_test\_1/quartus}  Stefan Tauner committed May 04, 2018 227 228 229 230 231  Set Cyclone III - EP3C16-F484-C6 as device \item Add the following files to the project \begin{plainlisting}[gobble=12]  Stefan Tauner committed May 04, 2018 232  fiji/de0_test_1/fiji/fiji\_top.vqm  Stefan Tauner committed May 04, 2018 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253  fiji/de0_test_1/fiji/tmr_vga_demo_constraints.quartus.qsf fiji/de0_test_1/quartus/fiji_top.sdc \end{plainlisting} \item Import the assignments from \begin{plainlisting}[gobble=12] boards/pins_de0.qsf fiji/de0_test_1/fiji_pins.qsf \end{plainlisting} The clock and pin constraints have already been entered for this demo. In a real'' project, you would have to manually enter them in Quartus. \item Perform Analysis and Synthesis'' \item Check the imported pin assignments in the Pin Planner \item Perform Full Compilation' \end{enumerate}  Stefan Tauner committed May 04, 2018 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 \subsubsection{Place-and-Route for Xilinx FPGAs} To create the final bitstream for Xilinx FPGAs the instrumented netlist needs to be placed and routed with Vivado as follows. Replace basys3 with your board name where applicable. \begin{enumerate} \item Start Vivado and create a new project (e.g., \texttt{fiji\_basys3}) in \texttt{fiji/basys3\_test\_1/vivado/}. \item Select Post-synthesis Project''. \item Add the instrumented netlist as source to the project: \begin{plainlisting}[gobble=12] fiji/basys3_test_1/synp/basys3/spriteflyer_top.vm \end{plainlisting} \item Add the following pre-defined constraint files: \begin{plainlisting}[gobble=12] boards/pins_basys3.xdc fiji/basys3_test_1/vivado/pins_fiji.xdc fiji/basys3_test_1/vivado/clock.xdc \end{plainlisting} The clock and pin constraints have already been entered for this demo. In a real'' project, you would have to manually enter them in Vivado. \item Set the respective FPGA device: \begin{itemize} \item Basys~3: \texttt{xc7a35tcpg236-1} \item Zybo: \texttt{xc7z010clg400-1} \end{itemize} \item Set \texttt{fiji\_top} as toplevel module. \item Execute Generate Bitstream'' (in the Flow Navigator'' on the left on the bottom). \end{enumerate}  Stefan Tauner committed May 04, 2018 291 292 293 \subsection{Runtime Fault Injection} \begin{enumerate}  Stefan Tauner committed May 04, 2018 294  \item Download the FPGA bitstream with the FPGA vendor tool  Stefan Tauner committed May 04, 2018 295  \item Run the \ac{FIJIEE} GUI  Stefan Tauner committed May 04, 2018 296 297 298 299  % \begin{lstlisting}[style=shell,gobble=12] % $perl ../../../bin/fiji_ee_gui.pl -s fiji/de0_test_1/fiji/tmr_vga_demo_download.cfg \ % -t fiji/de0_test_1/fiji/tmr_vga_demo_test.tst % \end{lstlisting}  Stefan Tauner committed May 04, 2018 300  \begin{lstlisting}[style=shell,gobble=12]  Stefan Tauner committed May 04, 2018 301 $ perl ../../../bin/fiji_ee_gui.pl -s fiji/de0_test_1/fiji/tmr_vga_demo_download.cfg  Stefan Tauner committed May 04, 2018 302  \end{lstlisting}  Stefan Tauner committed May 04, 2018 303 304 305 306 307 308 309  \item Execute tests at will % \item Execute tests: % \begin {itemize} % \item Pre-defined sequence in \texttt{fiji/de0\_test\_1/fiji/tmr\_vga\_demo\_test.tst} % \item Manual tests % \item Random tests % \end {itemize}  Stefan Tauner committed May 04, 2018 310 311 312 313 314 315 316 317 318 319 320 \end{enumerate} When the \emph{\ac{TMR} Enable} switch is in 0'' position, the output from \ac{TMR} domain 0 is directly relayed to the \ac{VGA} output. All faults are directly visible. The fault detection LEDs remain dark. When the \emph{\ac{TMR} Enable} switch is in 1'' position, the \ac{VGA} output is generated by majority voting over the three \ac{TMR} domains. Faults in \ac{TMR} domain 0 are masked and thus are not visible. When \ac{TMR} is enabled, the LEDs on the board show (1) if an error is detected by the voter (one domain disagrees with the others) and (2) in which voter (Red, Green, Blue) the error is detected.