Netlist.pm 54.7 KB
Newer Older
1
2
#** @file Netlist.pm
# @verbatim
Christian Fibich's avatar
Christian Fibich committed
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
#-------------------------------------------------------------------------------
#  University of Applied Sciences Technikum Wien
#
#  Department of Embedded Systems
#  http://embsys.technikum-wien.at
#
#  Josef Ressel Center for Verification of Embedded Computing Systems
#  http://vecs.technikum-wien.at
#
#-------------------------------------------------------------------------------
#  File:              Netlist.pm
#  Created on:        29.04.2015
#  $LastChangedBy$
#  $LastChangedDate$
#
#  Description:
#
20
#  FIJI Netlist class: Functions to instrument & export a Verilog::Netlist
Christian Fibich's avatar
Christian Fibich committed
21
#-------------------------------------------------------------------------------
22
23
# @endverbatim
#*
Christian Fibich's avatar
Christian Fibich committed
24

Christian Fibich's avatar
Christian Fibich committed
25
26
27
28
29
## @file Netlist.pm
# @brief Contains class \ref FIJI::Netlist

## @class FIJI::Netlist
# @brief Functions to instrument & export a Verilog::Netlist
30
31
32
33
package FIJI::Netlist;

use strict;
use warnings;
34
use diagnostics;
35

36
use Scalar::Util 'blessed';
37
use Log::Log4perl qw(get_logger :easy);
38
use File::Basename qw(basename);
39

40
41
use Verilog::Netlist 99.415;
use Verilog::Language 99.415;
42
43
44
45
use Data::Dumper;

use FIJI::VHDL;

46
use constant HIERSEP               => "/";
47
use constant FIJI_NAMESPACE_PREFIX      => "fiji_";
Christian Fibich's avatar
Christian Fibich committed
48
49
use constant FIJI_PORT_IN_POSTFIX  => "_inj_i";
use constant FIJI_PORT_OUT_POSTFIX => "_ori_o";
50
use constant MAX_UNIQUE_TRIES => 10;
51

Christian Fibich's avatar
Christian Fibich committed
52
use constant FIJI_LOGO => <<logo_end;
53
54
55
56
57
58
//  FIJIFIJIFIJIFIJIFIJIFIJIFIJIFIJIFIJIFIJI
//  FIJIFIJIFIJIFIJIF   FIJIFIJIFIJIFIJIFIJI
//  FIJIFIJIFIJIFIJ    IFIJIFIJIFIJIFIJIFIJI
//  FIJIF       FI           IJIFIJIFIJIFIJI
//  FIJIFIJIFI            JIFIJIFIJIFIJIFIJI
//  FIJIFIJI            FIJIFIJIFIJIFIJIFIJI
59
60
//  FIJIFI    JI   IFI   IJIFIJIFIJIFIJIFIJI
//  FIJIF   FIJ   JIFIJ   JIFIJIFIJIFIJIFIJI
61
62
63
64
65
66
67
68
69
70
//  FIJIFIJIFI   IJIFIJI   IFIJIFIJIFIJIFIJI
//  FIJIFIJIF    IJIFIJIFIJIFIJIFIJIFIJIFIJI
//  FIJIFIJI    FIJIFIJIFIJIFIJIFIJIFIJIFIJI
//  FIJIFIJ     FIJIF           FIJIFIJIFIJI
//  FIJIFI     IFI      Fault      IFIJIFIJI
//  FIJIF             InJection     FIJIFIJI
//  FIJ              Instrumenter    IJIFIJI
//  F                                    IJI
//  FIJIFIJIFIJIFIJIFIJIFIJIFIJIFIJIFIJIFIJI
logo_end
71

72
73
## @function public new ()
# @brief creates a new FIJI::Netlist object
Christian Fibich's avatar
Christian Fibich committed
74
#
75
76
# @returns the newly created FIJI::Netlist object
sub new {
Christian Fibich's avatar
Christian Fibich committed
77

78
    my ($class) = @_;
Christian Fibich's avatar
Christian Fibich committed
79

80
81
    my $self = {};
    bless $self, $class;
Christian Fibich's avatar
Christian Fibich committed
82

83
    $self->{'nl'} = new Verilog::Netlist(
Christian Fibich's avatar
Christian Fibich committed
84

85
86
87
88
89
90
        # options => $opt,
        # keep_comments => 1, # include comments in netlist
        link_read_nonfatal => 1,    # do not fail if module description not found
        use_vars           => 1,
    );
    return $self;
91
92
}

93
94
95
96
97
98
99
100
## @method public read_file ($filename)
# @brief Tries to read a Verilog netlist from the given file
#
# @param filename    The Verilog file to read
#
# @returns 1   if an error occurred
# @returns 0   if successful
sub read_file {
101
    my $logger = get_logger("");
Christian Fibich's avatar
Christian Fibich committed
102
    my ($self, $filename) = @_;
103

104
105
    ## Netlist synthesized from VHDL could contain SV keywords at this point.
    Verilog::Language::language_standard("1364-2001");
106

107
    $logger->info("Reading in netlist from file \"$filename\".");
108
    eval {
Christian Fibich's avatar
Christian Fibich committed
109
110
        $self->{'nl'}->read_file(filename => $filename);    # read Verilog file
        $self->{'nl'}->link();                              # Read in any sub-modules
111
    };
112

Christian Fibich's avatar
Christian Fibich committed
113
114
    if ($self->{'nl'}->errors() != 0 || $@) {
        $logger->error("Could not parse $filename!", $@ ? "\n" . $@ : "");
115
116
        return 1;
    }
117

118
    $self->{'filename'} = $filename;
119

120
121
    $logger->info("Successfully read in netlist from file \"$filename\".");
    return 0;
122
123
}

124
125
126
127
128
## @method public get_toplevel_port_names ()
# @brief retrieves the port names of all toplevel modules
#
# @returns an array of Verilog::Port references
sub get_toplevel_port_names {
Christian Fibich's avatar
Christian Fibich committed
129
    my ($self, $dir) = @_;
130
    my $ports_ref = [];
Christian Fibich's avatar
Christian Fibich committed
131
    foreach my $mod ($self->{'nl'}->top_modules_sorted) {
132
        foreach my $port ($mod->ports) {
Christian Fibich's avatar
Christian Fibich committed
133
134
135
136
            if (   !defined($dir)
                || ($dir eq "o" && $port->direction eq "out")
                || ($dir eq "i" && $port->direction eq "in"))
            {
Christian Fibich's avatar
Christian Fibich committed
137
138
                push @{$ports_ref}, $port->name;
            }
139
140
141
        }
    }
    return $ports_ref;
142
143
}

Christian Fibich's avatar
Christian Fibich committed
144
145
146
147
148
149
## @method public get_toplevel_module ()
# @brief retrieves the port names of all toplevel modules
#
# @returns a Verilog::Module reference
sub get_toplevel_module {
    my ($self) = @_;
Christian Fibich's avatar
Christian Fibich committed
150
151
152
153
154
    my @m      = $self->{'nl'}->top_modules_sorted;
    my $n      = @m;
    return $m[0] if ($n == 1);
    return "More than one toplevel module present in netlist." if ($n > 1);
    return "No toplevel module found.";
Christian Fibich's avatar
Christian Fibich committed
155
156
}

157
158
159
160
## @method public get_nets ()
# @brief retrieves all nets in the netlist
#
# @returns an array of hashes for all nets containing:
161
162
163
# 'name' the name of the net
# 'path' the hierarchical path of the net
# 'net'  the Verilog::Netlist::Net reference to the net
164
sub get_nets {
165
166
167
168
169
    my ($self) = @_;

    # my $nets_ref = {'metadata' => [], 'names' => [], 'nets' => []};
    my $nets_ref = [];
    my $hier     = "";
170
171
172
    my $top      = $self->get_toplevel_module();
    if ($top->isa("Verilog::Netlist::Module")) {
        $self->_get_subnets($nets_ref, $top, $hier);
173
174
    }
    return $nets_ref;
175
176
}

177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
sub _extract_low_high {
    my ($in_low, $in_high) = @_;
    my ($out_low, $out_high);

    # msb might be lower than lsb if index range is "upto" -> swap
    if ($in_high < $in_low) {
        $out_low = $in_high;
        $out_high = $in_low;
    } else {
        $out_low = $in_low;
        $out_high = $in_high;
    }
    return ($out_low, $out_high);
}

192
193
194
195
196
197
198
199
200
#** @method private _get_subnets ($nets_ref,$mod,$hier)
# @brief retrieves all nets in the given module
#
# @param nets_ref    the central reference to push found nets (name,path,netref) to
# @param mod         the module to search
# @param hier        a string representing the current hierarchy level, separated
#                    be HIERSEP
sub _get_subnets {

201
    my $logger = get_logger("");
202
    my ($self, $nets_ref, $mod, $hier, $instname) = @_;
203

204
    my $thishier = $hier;
Christian Fibich's avatar
Christian Fibich committed
205
    $thishier .= HIERSEP if $thishier ne "";
206
207
208
209
210
    if (defined $instname) {
        $thishier .= $instname;
    } else {
        $thishier .= $mod->name;
    }
211

Christian Fibich's avatar
Christian Fibich committed
212
    foreach my $n ($mod->nets) {
213
        if (defined($n->msb) && defined($n->lsb)) {
214
            my ($low, $high) = _extract_low_high($n->lsb, $n->msb);
215
            for (my $sub = $low ; $sub <= $high ; $sub++) {
Christian Fibich's avatar
Christian Fibich committed
216
                my $thisnet_ref = {name => $n->name . "[$sub]", path => $thishier, net => $n, index => $sub};
217
218
219
220
221
222
223
                push(@{$nets_ref}, $thisnet_ref);
            }
        } else {
            my $thisnet_ref = {name => $n->name, path => $thishier, net => $n};
            push(@{$nets_ref}, $thisnet_ref);
        }

224
    }
225

226
    foreach my $cell ($mod->cells) {
Christian Fibich's avatar
Christian Fibich committed
227
        if (defined($cell->submod)) {
228
            $self->_get_subnets($nets_ref, $cell->submod, $thishier, $cell->name);
229
        }
230
231
232
    }
}

233
234
235
## @function private _check_name_in_hierarchy ($startmod,$name)
# @brief checks if a given name exists
# checks if the $name exists as port, net, or cell name in the instantiation tree.
236
#
237
238
# @param startmod    the module to start with
# @param name        the name to check against
239
sub _check_name_in_hierarchy {
240

241
    my $logger = get_logger("");
Christian Fibich's avatar
Christian Fibich committed
242
    my ($startmod, $name) = @_;
243
244
    my $nl = $startmod->netlist;

245
    $logger->debug("Checking \"" . $startmod->name . "\" for name \"$name\"");
246
247

    # check if a net is named the same
248
    for my $net ($startmod->nets) {
Christian Fibich's avatar
Christian Fibich committed
249
        if ($net->name eq $name) {
250
            my $msg = "Name \"$name\" does already exist as net in " . $startmod->name;
251
            return $msg;
252
253
254
255
        }
    }

    # check if a port is named the same
256
    for my $port ($startmod->ports) {
Christian Fibich's avatar
Christian Fibich committed
257
        if ($port->name eq $name) {
258
            my $msg = "Name \"$name\" does already exist as port in " . $startmod->name;
259
            return $msg;
260
261
262
        }
    }

263
    for my $cell ($startmod->cells) {
Christian Fibich's avatar
Christian Fibich committed
264
        if ($cell->name eq $name) {
265
            my $msg = "Name \"$name\" does already exist as cell in " . $startmod->name;
266
            return $msg;
267
268
269
270
        }
    }

    # find any module instantiating the current start module
271
272
    foreach my $mod ($nl->modules) {
        foreach my $cell ($mod->cells) {
Christian Fibich's avatar
Christian Fibich committed
273
274
            if (defined $cell->submod && $cell->submod == $startmod) {
                my $msg = _check_name_in_hierarchy($mod, $name);
275
                return $msg if defined $msg;
276
277
278
            }
        }
    }
279

280
    return undef;
281
282
}

283
284
## @function private _add_port_to_hierarchy ($startmod,$name,$function,$index,$indent)
# @brief adds a port to all modules starting from a leaf node
285
#
286
287
288
289
290
291
292
293
# @param startmod    the module to start with
# @param name        the port name to be generated
# @param function    the function of this port in FIJI (FIJI::VHDL->FIJI_PORTTYPE_xxx)
# @param index       for ORIGINAL,MODIFIED and FAULT_DETECT: the index of this net
# @param indent      optional, needed just for formatting logging output
#
# @returns undef if the given port $name is already found
# @returns Verilog::Port reference to the new port if successful
Christian Fibich's avatar
Christian Fibich committed
294
sub _add_port_to_hierarchy {
295

296
    my $logger = get_logger("");
Christian Fibich's avatar
Christian Fibich committed
297
    my ($startmod, $name, $function, $index, $indent) = @_;
298
    my $nl        = $startmod->netlist;
299
    my $direction = "undef";
Christian Fibich's avatar
Christian Fibich committed
300
    if (!defined $indent) {
301
302
303
304
305
        $indent = "";
    } else {
        $indent .= "  ";
    }

Christian Fibich's avatar
Christian Fibich committed
306
    return undef if ($startmod->find_port($name));
307

308
    $logger->debug($indent . "Adding port \"$name\" to module \"" . $startmod->name . "\"");
309
310

    # decide direction
311
    if (   $function == FIJI::VHDL->FIJI_PORTTYPE_MODIFIED
Christian Fibich's avatar
Christian Fibich committed
312
        || $function == FIJI::VHDL->FIJI_PORTTYPE_RESET_TO_DUT)
313
    {
314
        $direction = "in";
315
    } else {
316
317
318
319
        $direction = "out";
    }

    # generate port
Christian Fibich's avatar
Christian Fibich committed
320
    my $np = $startmod->new_port(name => $name, direction => $direction);
321
322

    # set port type for wrapper generation
Christian Fibich's avatar
Christian Fibich committed
323
    $np->userdata(FIJI::VHDL->FIJI_USERDATA_PORTTYPE, $function);
324
325

    # set indices
326
    if (   $function == FIJI::VHDL->FIJI_PORTTYPE_MODIFIED
Christian Fibich's avatar
Christian Fibich committed
327
        || $function == FIJI::VHDL->FIJI_PORTTYPE_ORIGINAL)
328
    {
Christian Fibich's avatar
Christian Fibich committed
329
330
331
        $np->userdata(FIJI::VHDL->FIJI_USERDATA_FIU_INDEX, $index);
    } elsif ($function == FIJI::VHDL->FIJI_PORTTYPE_FAULT_DETECTION) {
        $np->userdata(FIJI::VHDL->FIJI_USERDATA_FD_INDEX, $index);
332
333
    }

Christian Fibich's avatar
Christian Fibich committed
334
335
    # let Verilog-Perl create a new net for the new port.
    $startmod->link;
336
337

    # find all modules instantiating the current module
Christian Fibich's avatar
Christian Fibich committed
338
    foreach my $mod ($nl->modules_sorted) {
339
        foreach my $cell ($mod->cells) {
Christian Fibich's avatar
Christian Fibich committed
340
            if (defined $cell->submod && $cell->submod == $startmod) {
341
342
                $logger->debug($indent . "Adding pin \"$name\" to cell \"" . $cell->name . "\"");
                $logger->debug($indent . "Connecting pin \"" . $cell->name . HIERSEP . $name . "\" to port \"" . $np->module->name . HIERSEP . $np->name . "\"");
343
344
345
                $cell->new_pin(
                    name     => $name,
                    portname => $np->name,
346
                    netnames => [{'netname' => $np->net->name}],
347
348
                );

Christian Fibich's avatar
Christian Fibich committed
349
                # let verilog-perl find the net and port.
Christian Fibich's avatar
Christian Fibich committed
350
                # @FIXME sufficient to link "mod" here?
Christian Fibich's avatar
Christian Fibich committed
351
                $mod->link;
Christian Fibich's avatar
Christian Fibich committed
352
                _add_port_to_hierarchy($mod, $name, $function, $index, $indent);
353
354
355
            }
        }
    }
356

357
358
359
    return $np;
}

360
361
362
## @method public net_add_function($net, $function, $port_name, $index)
# @brief Generate external access to a single net
#
Christian Fibich's avatar
Christian Fibich committed
363
364
365
366
367
368
# Performs the following steps:
#    1.  check if the default port name does not yet exist
#    1a. if it exists, generate a new net name
#    2.  add a port through the entire hierarchy
#    3.  assign the net to the port using a contassign statement
#
369
370
371
372
373
374
375
# @param net         the Verilog::Net object to be used
# @param function    the function out of FIJI::VHDL->FIJI_PORTTYPE_xxx
# @param port_name   how the port shall be named (will be prefixed with "fiji_")
# @param index       for some FIJI_PORTTYPEs, an index is needed (FIU and Fault Detect)
#
# @returns undef
sub net_add_function {
376
    my $logger = get_logger("");
Christian Fibich's avatar
Christian Fibich committed
377
    my ($self, $net, $function, $port_name, $index) = @_;
378

379
    $logger->debug("Adding function to \"" . $net->module->name . "\", net \"" . $net->name . "\"");
380
381

    my $prefix = "fiji_";
382
383
384
385
386

    my $unique_name = _unique_name($net->module,$prefix.$port_name);

    if (!defined $unique_name) {
        $logger->error("Could not find a unique name for prefix ".$prefix.$port_name)
387
388
    }

389
390
    $logger->debug("\"" . $unique_name . "\" can be used as fiji connector");
    my $op = _add_port_to_hierarchy($net->module, $unique_name, $function, $index);
391

392
    $logger->debug("Connecting Port \"" . $op->name . "\" to net \"" . $net->name . "\"");
393

Christian Fibich's avatar
Christian Fibich committed
394
    # connect the net to the newly created port
395
396
397
398
399
400
401
    $net->module->new_contassign(
        keyword => "assign",
        lhs     => $op->name,
        rhs     => $net->name,
        module  => $op->module,
        netlist => $op->module->netlist
    );
402

403
404
405
    return undef;
}

406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
# tries to generate a unique but recognizable net name by appending a
# random hex number if necessary
sub _unique_name {
    my $logger = get_logger("");
    my ($mod,$requested_name) = @_;

    # check if requested name is OK
    my $msg = _check_name_in_hierarchy($mod, $requested_name);
    
    if (!defined $msg) {
        return $requested_name;
    }

    # else try up to 10 times to generate a unique name by appending
    # a 4-digit random hex number
    for (my $tries = 0; $tries < MAX_UNIQUE_TRIES; $tries++) {
        my $name = sprintf("%s_%04x", $requested_name, rand(0xffff));
        $msg = _check_name_in_hierarchy($mod, $name);
        return $name if (!defined $msg);
    }
    
    return undef
}

430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
# take a possible escaped identifier and make it a legal _and_ sane verilog identifier
sub _sanitize_identifier {
    my $insane = shift;

    # Verilog allows "non-alphanumeric" characters in identifiers if they start with a backslash and end with whitespace (escaped identifiers) but we don't want to.
    my $sane = ($insane =~ s/[^a-zA-Z0-9_]+/_/gr);
    # VHDL signals must not contain multiple subsequent underscores
    $sane =~ s/__+/_/g;
    return $sane
}

sub generate_contassign {
    my $logger = get_logger("");
    my ($module, $lhs, $rhs) = @_;
    $logger->trace("Setting \"$lhs = $rhs\"");
    $module->new_contassign(
        keyword => "assign",
        lhs     => $lhs,
        rhs     => $rhs,
        module  => $module,
        netlist => $module->netlist
    );
}

454
455
456
457
## @method public instrument_net($net,$fiu_idx, $driver, $driver_type)
# @brief instruments a single net for fault injection
#
# This method performs the following steps
458
459
460
#   1. determine the connected objects (driver as well as driven nets, pins etc)
#   2. generate external access output and input ports and intermediate nets
#   3. interconnect these ports to the matching driver and driven cells via the intermediate nets
Christian Fibich's avatar
Christian Fibich committed
461
#
462
# @param net_path        the Verilog::Net to instrument
463
# @param fiu_idx         the FIU number this external access shall be connected to
464
465
# @param driver_path     the path to the driver of this net (optional but depends on driver_type)
# @param driver_type     the type of the driver (can be PIN, PORT, ASSIGN) (optional but depends on driver_path)
466
467
468
469
#
# @returns STRING          if an error occurred
# @returns undef           if successful
sub instrument_net {
470

471
    my $logger = get_logger("");
472
    my ($self, $net_path, $fiu_idx, $driver_path, $driver_type) = @_;
473

474
    # split hierarchical net path
475
    my $net_descriptor = $self->get_netdescriptor_from_path($net_path);
476
477

    if (ref($net_descriptor) ne "HASH") {
478
        return $net_descriptor;
479
480
481
    }

    my $net = $net_descriptor->{'net'};
482
    my $net_name = $net_descriptor->{'net_name'};
483
484
    my $msb = $net_descriptor->{'msb'};
    my $lsb = $net_descriptor->{'lsb'};
485
    my $mod = $net_descriptor->{'mod'};
486
487
488
    my $idx = '';
    my $idx_postfix = '';

489
490
491
492
493
494
    # We need to produce names for the i/o ports that route the signals
    # to the FIC. To allow to instrument multiple indices of a single
    # signal we need to make these names unique thus we even include the
    # indices if used.
    if (defined $msb && defined $lsb) {
        if ($msb ne $lsb) {
495
            # We dont support the instrumentation of vectors (only sinlge indices of busses).
496
            return "The given net to instrument is a vector with multiple bits.\nThis is not supported.\nMaybe you want to instrument a single bit of said vector instead?";
497
498
            # $idx         = "[".$msb.":".$lsb."]";
            # $idx_postfix = "_".$msb."_".$lsb."_";
499
        } else {
500
501
            $idx         = "[".$msb."]";
            $idx_postfix = "_".$msb."_";
502
503
504
        }
    }

505
    $logger->info("Instrumenting \"" . $net->module->name . "\", net \"" . $net->name.$idx . "\"");
506

507
508
509
510
511
    # we want to perceive the connection state before any changes (at least w/o changes by this invocation)
    my %connections;
    my $rv = $self->_get_net_connections($net, \%connections, $msb, $driver_path, $driver_type);
    return $rv if (defined $rv);

512
513
514
515
    my $output_name = (FIJI_NAMESPACE_PREFIX . $net->name . $idx_postfix . FIJI_PORT_OUT_POSTFIX);
    $output_name = _sanitize_identifier($output_name);
    my $input_name  = (FIJI_NAMESPACE_PREFIX . $net->name . $idx_postfix . FIJI_PORT_IN_POSTFIX);
    $input_name = _sanitize_identifier($input_name);
516

517
    # generate unique name for output port, return with error message if that fails
518
    my $unique_output_name = _unique_name($mod, $output_name);
519
    return "Could not generate unique name for prefix $output_name" if (!defined $unique_output_name);
520

521
    $logger->debug("\"" . $unique_output_name . "\" will be used as fiji connector (output)");
522
    my $op = _add_port_to_hierarchy($mod, $unique_output_name, FIJI::VHDL->FIJI_PORTTYPE_ORIGINAL, $fiu_idx);
523

524
525
    # generate unique name for input port, return with error message if that fails
    my $unique_input_name = _unique_name($mod, $input_name);
526
    return "Could not generate unique name for prefix $input_name" if (!defined $unique_input_name);
527

528
    $logger->debug("\"" . $unique_input_name . "\" will be used as fiji connector (input)");
529
    my $ip = _add_port_to_hierarchy($mod, $unique_input_name, FIJI::VHDL->FIJI_PORTTYPE_MODIFIED, $fiu_idx);
530

Christian Fibich's avatar
Christian Fibich committed
531

532
533
534
    # Add an intermediate net to allow patching without rewriting connections everywhere
    #
    # We use the requested signal as sink/destination.
535
    # That way we only need to change the driver to drive our intermediate net.
536
    #
537
538
539
    # We first generate a suitable name for the intermediate net,
    # then change the driver accordingly and handle other aspects of
    # the intermediate net at the very bottom of this function.
540

541
    # Choose intermediate net name
542
    my $net_name_tmp = _sanitize_identifier(FIJI_NAMESPACE_PREFIX . $net_name . "_in_tmp");
543
    my $name_check = _check_name_in_hierarchy($mod, $net_name_tmp);
544

545
546
547
    # Switch the driver from the original signal to the intermediate net.
    my $driver_is_vector = 0;
    my $driver_is_port = 0;
548
    foreach my $connection (@{$connections{'drivers'}}) {
Christian Fibich's avatar
Christian Fibich committed
549
        if (ref($connection) eq "Verilog::Netlist::Pin") {
550
551
552
            # If the driver is a pin of a (sub)cell, connect this pin to the intermediate net
            $logger->debug("Connecting (output) pin \"" . $connection->cell->name . HIERSEP . $connection->name . "\" to intermediate net \"$net_name_tmp\"");
            # FIXME: do concatenations really work? They are apparently split already by Verilog::perl but...
553
            for my $netname (@{$connection->netnames}) {
554
                if ($netname->{'netname'} eq $net->name) {
555
556
                    $netname->{'netname'} = $net_name_tmp; # FIXME: do we need to force a re-link (by deleting $connection->nets)?
                    # This net is a vector if the underlying net is a bus and we do not just select a single bit
557
558
559
560
                    # If driver is a vector we need a vectored intermediate bus.
                    # This is the case if
                    #   - the underlying net is a vector and there are no indices
                    #   - the underlying net is a vector and there are two different indices
561
                    if (defined($net->msb) && (!defined($netname->{'msb'}) || $netname->{'msb'} != $netname->{'lsb'})) {
562
                        $driver_is_vector = 1;
563
564
565
566
                    } else {
                        # Make sure we do not output the index unnecessarily (if the driver is a single bit of a vector)
                        undef($netname->{'msb'});
                        undef($netname->{'lsb'});
567
                    }
568
                }
569
            }
570
571
572
            # $connection->port(undef);    # resolved by link
        } else {
            if (ref($connection) eq "Verilog::Netlist::Port") {
573
574
575
576
577
                $driver_is_port = 1;
                # If instrumented net is a vector we will need an intermediate bus
                if (defined($net->msb)) {
                    $driver_is_vector = 1;
                }
578
579
580
581
                # If we are changing the name of a port of the top module we need to inform the VHDL generator
                if ($mod->is_top) {
                        $connection->userdata(FIJI::VHDL->FIJI_USERDATA_PREV_PORTNAME, $connection->name);
                }
582
583
584
585
586
587
588
589
                # Change type of existing non-instrumented input to wire -
                # practically transforming it to an ordinary wire that can easily be intrumented.
                $logger->debug("Transforming previous port named \"". $connection->name . "\" into an ordinary wire");
                $connection->net->decl_type(undef);
                $connection->net->net_type("wire");
                # Unsetting the port<->net inter-references forces their automatic re-setting at link time
                $connection->net->port(undef);
                $connection->net(undef);
590
                # Eventually connect this port to the intermediate net by changing its name
591
                $logger->debug("Connecting (input) port \"" . $connection->name . "\" to intermediate net \"$net_name_tmp\"");
592
                $connection->name($net_name_tmp); # NB: this will automatically change the cell's configuration on the next link() call.
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
            } elsif (ref($connection) eq "Verilog::Netlist::ContAssign") {
                # FIXME: concatenations
                # If the driver is an assignment, replace the LHS with the intermediate net
                if(0) {
                    $logger->debug("Connecting to intermediate net \"" . $net_name_tmp . "\" the continuous assignment of \"" . $connection->rhs . "\"");
                    $connection->lhs($net_name_tmp);
                } else {
                    # Retrieve net object of LHS of the assignment to determine if it is a bus and if the assignment is to the complete net or a single bit.
                    my $lhs_elems = $self->_extract_netstring_elements($connection->lhs);
                    my $lhs_net_name = $lhs_elems->{'net_name'};
                    my $lhs_net = $mod->find_net($lhs_net_name);
                    if (!defined($lhs_net)) {
                        my $lhs_port = $mod->find_port($lhs_net_name);
                        if (!defined($lhs_port)) {
                            return "Could not find net or port in module \"" . $mod->name . "\" matching LHS of assignment \"" . $connection->lhs . "\" = \"" . $connection->rhs . "\"";
                        }
                        # FIXME: so this is actually a port...
                        $logger->fatal("Found port name in continuous assignment. This is not supported yet.");
                        return "BORKED";
                    }
613
614
615
616
617
618
619
620
621
622
623
624
625
626
                    my $rhs_elems = $self->_extract_netstring_elements($connection->rhs);
                    my $rhs_net_name = $rhs_elems->{'net_name'};

                    my $rhs_net = $mod->find_net($rhs_net_name);
                    # If driver is a vector we need a vectored intermediate bus.
                    # This is the case if on the RHS
                    #   - the underlying net is a vector and there are no indices
                    #   - the underlying net is a vector and there are two different indices
                    if (defined($rhs_net->msb) && (!defined($rhs_elems->{'msb'}) || ($rhs_elems->{'msb'} != $rhs_elems->{'msb'}))) {
                        $driver_is_vector = 1;
                    }
                    $logger->debug("Connecting to intermediate net \"" . $net_name_tmp . "\" the continuous assignment of \"" . $connection->rhs . "\"");
                    $connection->lhs($net_name_tmp);
                     if(1) {} else {
627
628
629
630
631
632
                        # If LHS is a bus however we need to drive the bit we want to instrument only
                        $logger->debug("Connecting to intermediate net \"" . $net_name_tmp."[".$msb."]" . "\" the continuous assignment of \"" . $connection->rhs . "\"");
                        $connection->lhs($net_name_tmp."[".$msb."]");
                        # $logger->debug("Connecting to non-instrumented bits of the intermediate net \"" . $connection->lhs."[".$msb."]" . "\" the continuous assignment of \"" . $net_name_tmp."[".$msb."]" . "\"");
                        # generate_contassign($mod, $connection->lhs."[".$msb."]", $net_name_tmp."[".$msb."]");
                    }
633
634
                }
            } else {
635
                $logger->debug("Driver instance is neither pin, port nor contassign?");
636
            }
637
638
        }
    }
639

640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
    # Below we create the intermediate net as needed.
    # A suitable name for the tmp net was already determined.
    # 1.) Generate the tmp net.
    # 2.) Assign injected signal from input pin to original signal.
    # 3.) If original signal is a bus forward orignal data from tmp net to untouched bits of original signal
    # 4.) Forward (injected bit of) intermediate net to FIC by assigning it to the output pin
    #
    # If the name is already taken then assume we need to instrument another bit of a bus
    # FIXME: maybe we should try harder to find out the reason why _check_name_in_hierarchy failed
    if (defined($name_check)) {
        if (!defined($net->msb)) {
            my $err = "Tried to instrument non-vector signal (\"$net_name\") twice or we really have a naming conflict.";
            $logger->error($err);
            return $err;
        }
        # We need to undo the previous assignment of the respective bit
        foreach my $statement ($mod->statements) {
            if ($statement->rhs =~ /^[ \t]*~?[ \t]*\Q$net_name_tmp\E(\[(\Q$msb\E)\])?$/) {
                $logger->debug("    unassigning \"" . $statement->lhs . " = " . $statement->rhs . "\"");
                $statement->delete();
            }
        }

        $logger->debug("    reassigning \"" . $net_name."[".$msb."] = " . $ip->net->name . "\"");
        generate_contassign($mod, $net_name."[".$msb."]", $ip->net->name);
665
        $driver_is_vector = 1;
666
667
    } else {
        # 2.) Generate intermediate (tmp) net for easier input and output routing
668
669
670
        # For ports we don't need to do that ourselves because Verilog::Perl will
        # generate a new apropriate net when linking the port.
        if ($driver_is_port) {
671
            $logger->debug("Intermediate port named \"" . $net_name_tmp . (defined($net->msb) ? "[" . $net->msb .":". $net->lsb . "]" : "") . "\" to patch \"$net_name\" will be generated automatically later");
672
        } else {
673
674
675
676
677
678
679
680
681
682
683
684
685
686
            # If the driver is a vector then we will generate a vectored intermediate net as well.
            # However, if the driver is a single-bit net or a single bit of a vector we generate
            # a simple intermediate net (and could get away with none at all actually).
            my @net_cfg = (name => $net_name_tmp);
            if ($driver_is_vector) {
                $logger->debug("Generating intermediate wire named \"" . $net_name_tmp . "[" . $net->msb .":". $net->lsb . "]\" to patch \"$net_name\"");
                push(@net_cfg,
                    msb => $net->msb,
                    lsb => $net->lsb,
                );
            } else {
                $logger->debug("Generating intermediate wire named \"" . $net_name_tmp . "\" to patch \"$net_name\"");
            }
            $mod->new_net(@net_cfg);
687
688
689
690
691
692
693
694
695
696
        }

        # 3+4.) Assign injected (and uninjected bits of vectors) to previous signal.
        # Below we assign the altered signal from the FIC to the original signal.
        # For busses we need to connect all non-instrumented bits of the tmp net
        # additionally to preserve their unmodified values.

        if (!defined($net->msb)) {
            # If the instrumented net is not a vector we simply assign the injected signal
            generate_contassign($mod, $net_name, $ip->net->name);
697
        } elsif (!$driver_is_vector) {
698
699
700
701
702
703
            # If the net is a vector but the driver was driving only one bit
            # then we need to drive the originally driven bit only
            generate_contassign($mod, $net_name."[".$msb."]", $ip->net->name);
        } else {
            # For drivers of complete busses we need to connect all non-instrumented bits of the tmp net
            # additionally to preserve their unmodified values.
704
            my ($low, $high) = _extract_low_high($net->lsb, $net->msb);
705
706
707
708
709
710
711
712
713
714
715
            for (my $i = $low ; $i <= $high ; $i++) {
                if ($i == $msb) {
                    generate_contassign($mod, $net_name."[".$i."]", $ip->net->name);
                } else {
                    generate_contassign($mod, $net_name."[".$i."]", $net_name_tmp."[".$i."]");
                }
            }
        }
    }

    # 5.) Connect the tmp net to the output pin that forwards the signal to the FIC
716
717
    #     If the driver is not a vector a simple assignment is fine, else
    if (!$driver_is_vector) {
718
719
720
721
722
723
        $logger->debug("    assigning \"" . $op->net->name . " = " . $net_name_tmp . "\"");
        generate_contassign($mod, $op->net->name, $net_name_tmp);
    } else {
        $logger->debug("    assigning \"" . $op->net->name . " = " . $net_name_tmp ."[".$msb."]\"");
        generate_contassign($mod, $op->net->name, $net_name_tmp."[".$msb."]");
    }
724
    $mod->link;
725
726
727
    return undef;
}

728
729
730
## @method public validate_driver($net_path, $driver_path, $driver_type)
# @brief Check if the given driver is valid for the given net
#
731
732
# Check if the driver specified by $driver_type and $driver_path
# is actually connected to the net specified by $net_path
733
734
735
736
737
738
739
#
# @param net_path        The hierarchical path of the net, separeted by HIERSEP
# @param driver_path     The hierarchical path of the driver object, separated by HIERSEP
# @param driver_type     The type of the driver object, one of {PIN, PORT, ASSIGN}
#
# @returns STRING          if an error occurred
# @returns undef           if successfull
740
sub _validate_driver {
741
    my $logger = get_logger("");
Christian Fibich's avatar
Christian Fibich committed
742
    my ($self, $net_path, $driver_path, $driver_type) = @_;
743

Christian Fibich's avatar
Christian Fibich committed
744
    my $connection_object = $self->get_connection_object($driver_path, $driver_type);
745
    my $connections       = {};
746
    $self->_get_net_connections_from_path($net_path, $connections);
747

748
749
    goto FAIL if (!defined $connection_object);

Christian Fibich's avatar
Christian Fibich committed
750
751
    my @in_drivers     = grep { $_ == $connection_object } @{$connections->{'drivers'}};
    my @in_connections = grep { $_ == $connection_object } @{$connections->{'connected'}};
752

753
    goto FAIL if (@in_drivers == 0 && @in_connections == 0);
754
755

    return undef;
756
757
758
759
760

FAIL:
    my $msg = "No possible driver found";
    $logger->error($msg);
    return $msg;
761
762
}

763
764
765
766
767
768
769
770
771
## @function private _select_driver($connected,$net)
# @brief Prompt the user to select a driver for a net from a set of given cells/outputs
#
# @param connected       list reference containing connected Verilog::Perl instances
# @param net             the Verilog::Perl::Net instance to select the driver for
#
# @returns STRING          if an error occurred
# @returns Driver object   if successful
sub _select_driver {
Christian Fibich's avatar
Christian Fibich committed
772
    my ($connected, $net) = @_;
773

774
    print "Select driver for net " . $net->name . ": \n";
775
    my $di;
Christian Fibich's avatar
Christian Fibich committed
776
777
    for ($di = 0 ; $di < @{$connected} ; $di++) {
        printf("[%d] %s\n", $di, FIJI::Netlist->_connection_tostr(@{$connected}[$di]));
778
    }
Christian Fibich's avatar
Christian Fibich committed
779
    printf("[x] none of the above.\n", $di);
780
    my $sel;
781
    while (1) {
782
        $sel = <STDIN>;
Christian Fibich's avatar
Christian Fibich committed
783
        if ($sel =~ m/[0-9]+/ && defined @{$connected}[$sel]) {
784
            last;
Christian Fibich's avatar
Christian Fibich committed
785
        } elsif ($sel =~ m/[xX]/) {
786
            my $msg = "No driver selected for net " . $net->name;
787
            return $msg;
788
789
        } else {
            print "Invalid driver.\n";
790
791
792
        }
    }
    return @{$connected}[$sel];
793
794
}

795
796
797
## @method private _connection_tostr ($connection,$conn_str_list_ref)
# @brief Stringifies a connection information
#
Christian Fibich's avatar
Christian Fibich committed
798
# The string is in the format \<TYPE\>: \<PATH|TO|Netname\>
799
# Where '|' can be any HIERSEP and TYPE is one of {PIN, PORT, ASSIGN}
800
# and optionally pushes a hash {path=>...,type=>...,} onto the list @$conn_str_list_ref
801
#
802
803
804
# @param connection          the connection to print
# @param conn_str_list_ref   optional list where a hash describing the connection is pushed
#
Christian Fibich's avatar
Christian Fibich committed
805
# @returns STRING  in the format \<TYPE\>: \<PATH|TO|Netname\>
806
sub _connection_tostr {
Christian Fibich's avatar
Christian Fibich committed
807
    my ($self, $connection, $conn_str_list_ref) = @_;
808
809
    my $path;
    my $type;
810
    my $str;
811

Christian Fibich's avatar
Christian Fibich committed
812
    if (ref($connection) eq "Verilog::Netlist::Pin") {
813
        $path = $connection->cell->module->name . HIERSEP . $connection->cell->name . HIERSEP . $connection->name;
814
        $type = "PIN";
815
        $str = $type . ": " . $path
Christian Fibich's avatar
Christian Fibich committed
816
    } elsif (ref($connection) eq "Verilog::Netlist::Port") {
817
        $path = $connection->module->name . HIERSEP . $connection->name;
818
        $type = "PORT";
819
        $str = $type . ": " . $path
820
    } elsif (ref($connection) eq "Verilog::Netlist::ContAssign") {
821
        $path = $connection->module->name . HIERSEP . $connection->rhs;
822
        $type = "ASSIGN";
823
        $str = $type . ": " . $connection->rhs;
824
    }
825
826
    push @{$conn_str_list_ref}, {path => $path, type => $type} if defined $conn_str_list_ref;
    return $str
827
828
}

829
830
831
## @method public get_connection_object ($connection_path,$connection_type)
# @brief Retrieves the connection object specified by path and type
#
832
# Retrieves a reference to the Verilog::Pin, Verilog::Port or Verilog::ContAssign
833
834
835
836
837
# Object specified by the parameters
#
# @param connection_path     the hierarchichal PATH|To|the|object
# @param connection_type     the type of the object {PIN,PORT,ASSIGN}
#
838
# @returns the Verilog::Pin, Verilog::Port or Verilog::ContAssign Object specified by the parameters
839
sub get_connection_object {
840
    my $logger = get_logger("");
Christian Fibich's avatar
Christian Fibich committed
841
    my ($self, $connection_path, $connection_type) = @_;
842
843

    my $rv;
844
    my $SEP = HIERSEP;
845

Christian Fibich's avatar
Christian Fibich committed
846
    if ($connection_type eq "PIN") {
847
        if ($connection_path =~ /^(.+)\Q$SEP\E(.+)\Q$SEP\E(.+)$/) {
848

849
            $logger->trace("Looking for pin named \"$3\" in cell \"$2\" of module \"$1\"...");
850
851

            my $mod  = $self->{'nl'}->find_module($1);
Christian Fibich's avatar
Christian Fibich committed
852
853
            my $cell = $mod->find_cell($2) if (defined $mod);
            my $pin  = $cell->find_pin($3) if (defined $cell);
854
855
            $rv = $pin;
        }
Christian Fibich's avatar
Christian Fibich committed
856
    } elsif ($connection_type eq "PORT") {
857
        if ($connection_path =~ /^(.+)\Q$SEP\E(.+)$/) {
858

859
            $logger->trace("Looking for port named \"$2\" in module \"$1\"...");
860

861
            my $mod = $self->{'nl'}->find_module($1);
Christian Fibich's avatar
Christian Fibich committed
862
            my $port = $mod->find_port($2) if (defined $mod);
863
864
            $rv = $port;
        }
Christian Fibich's avatar
Christian Fibich committed
865
    } elsif ($connection_type eq "ASSIGN") {
866
        if ($connection_path =~ /^(.+)\Q$SEP\E(.+)$/) {
867
            my $net = $2;
868

869
            $logger->trace("Looking for assignment to/from \"$net\" in module \"$1\"...");
870
            my $mod = $self->{'nl'}->find_module($1);
871

Christian Fibich's avatar
Christian Fibich committed
872
            if (defined $mod) {
873
                my $assign;
874
                for my $a (grep { $_->isa("Verilog::Netlist::ContAssign") } $mod->statements) {
875
                    if ($a->lhs =~ /\Q$net\E/ || $a->rhs =~ /\Q$net\E/) {
876
                        $assign = $a;
877
                        $logger->trace(sprintf("Constant assignment: \"%s\" = \"%s\"", $a->lhs, $a->rhs));
878
879
880
                        last;
                    }
                }
881
                $rv = $assign;
882
883
884
            }
        }
    }
885
    $logger->warn("Could not find $connection_type \"$connection_path\"!") if !defined($rv);
886
    return $rv;
887
888
}

889

890
891
892
## @method private _get_net_connections ($net,$connection_hashref)
# @brief retrieves connections of a given net
#
893
# gets all pins, ports and assignments a net is connected to
894
#
895
# @param net_path               hierarchical path string of the net to be examined
896
897
898
899
900
# @param connection_hashref     a hashref where the results can be placed
#                               connection_hashref->{'drivers'} contains a list of driver cells
#                               connection_hashref->{'driven'} contains a list of driven cells
#                               connection_hashref->{'connected'} contains a list cells connected to the
#                               net but driver/driven cannot be decided
901
sub _get_net_connections_from_path {
902
    my $logger = get_logger("");
903
    my ($self, $net_path, $connection_hashref) = @_;
Stefan Tauner's avatar
Stefan Tauner committed
904
    my $net_descriptor = $self->get_netdescriptor_from_path($net_path);
905
906
    return $net_descriptor if (ref($net_descriptor) ne "HASH");
    my $net = $net_descriptor->{net};
907
    return $self->_get_net_connections($net, $connection_hashref, $net_descriptor->{'msb'});
908
909
910
911
912
913
}

## @method private _untie_concatenations ($concat, $arrayref)
# @brief breaks up a verilog concatenation into single net elements
#
# @param concat     string (including the {}) forming a verilog concatenation
914
# @return arrayref  array reference containing the individual concatenated verilog expressions in the given string
915
916
917
918
919
920
921
922
923
924
925
926
sub _untie_concatenations {
    my $logger = get_logger("");
    my ($self, $concat) = @_;

    if ($concat =~ /^\{(.+)\}$/) {
        $concat = $1;
    }
    my @net_strings;
    foreach my $net_string ($concat =~ /(.+)/g) {
        push(@net_strings, $net_string);
    }
    return \@net_strings;
927
}
928

929
930
931
932
933
934
935
## @method private _get_net_connections ($net,$connection_hashref)
# @brief retrieves connections of a given net
#
# gets all pins, ports and assignments a net is connected to
#
# @param net                    the net to be examined
# @param connection_hashref     a hashref where the results can be placed
936
937
938
#                               connection_hashref->{'drivers'} contains a list of things driving the net
#                               connection_hashref->{'driven'} contains a list of things driven by this net
#                               connection_hashref->{'connected'} contains a list things connected to the