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\section{Communication Protocol}
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\label{sec:comm_prot}
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The communication between the hardware and the \ac{FIJIEE} uses a
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UART protocol with 8N1 configuration (8 data bits, 1 stop bit, no parity).
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The baud rate is configurable (in \texttt{fiji\_setup.pl}) with a default of 115200.
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It works with any type of serial port (e.g., RS-232-compatible ports or USB-based TTL-level adapters) as long as the operating system represents it as such.
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Each communication direction uses its own message format as explained in the next two sections.
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\subsection{FIC to Host}
\label{sec:f2h}

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The data sent by the \ac{FIC} to the host serves to inform the host about important events and errors on the hardware side.
All packets consist of a single byte with three possible types encoded in bits 5 and 6 as depicted in \Cref{fig:f2h}.
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\begin{figure}[ht]
    \centering
    \input{content/protocol_fic_to_host}
    \caption{FIC to host communication message format}
    \label{fig:f2h}
\end{figure}


Bit 8 is used as even parity bit (i.e., it needs to be set iff an uneven
number of remaining bits are set).

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The three message types denoted by bits 5 and 6 inform the host about events that
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can happen at the transition between two execution phases:

\begin{itemize}
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    \item At the end of the configuration phase the \ac{FIC} acknowledges the
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          successful reception of the configuration data by sending a
          \textit{CONF\_DONE} message with all error bits set to zero.
          If there were any of the noted errors while the configuration
          was received the respective bits are set and the host is consequently informed about the issues.

    \item When the injection of \textit{FAULT1} starts, the temporary registers
          storing the configuration are freed and can be filled again
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          by the host. At that point the \ac{FIC} sends a \textit{READY} message
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          to inform the host that injection has been activated and that
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          a new configuration can be received by the \ac{FIC}.
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    \item If the injection phase \textit{FAULT1} ends before the host
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          has sent a new configuration, the \ac{FIC} indicates this case with
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          an \textit{UNDERRUN} message. In this case the exact timing
          of later injections depend on the point in time when the
          following configuration is received. 

\end{itemize}

Bits 3 and 4 contain the status of the two selected fault detection nets in the instrumented netlist.
This information can, for example, be used to stop a test run when the hardware detected a fault.

The lowest three bits denote possible errors when receiving configuration data from the host:

\begin{itemize}
    \item UART receive error
    \item Design ID mismatch
    \item CRC mismatch
\end{itemize}

They are only guaranteed to be valid in \textit{CONF\_DONE} messages as noted above.

\subsection{Host to FIC}
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\label{sec:h2f}
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The packets sent by the host are more complex as evident from \Cref{fig:h2f}.
They can be separated into two major parts:
configuration data for the \acp{FIU} and information destined for the \ac{FIC} itself.
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First, the configuration bits for the \acp{FIU} are transmitted in a serialized
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fashion: To end the actual data at a byte boundary the first bits are used
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as stuffing, if need be. Then the data for the last \ac{FIU} follows succeeded
by the configuration for the \ac{FIU} before the last etc. At byte borders the
data of a single \ac{FIU} is simply split and continued to be transmitted in
the next byte. Each 6-bit \ac{FIU} configuration consists of two 3-bit fault
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patterns, of which the pattern transferred first (1) is activated in phase
\textit{FAULT1}, while the second pattern (2) is activated in \textit{FAULT2}.
Each bit pattern is transferred with the least significant bit first.

The remaining part of the message contains control information destined
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to the \ac{FIC} itself. All multi-byte values are transmitted in little-endian
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(on the byte and bit level). At first, the load values of the two
timers for the FAULT phases (duration $t_1$ for \textit{FAULT1} and duration $t_2$
for \textit{FAULT2} respectively) are transmitted. The number of bytes
required depends on the width of the timers and can vary between designs.

Following the timer values a bit field is sent to control the following properties:

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\begin{description}[leftmargin=5.5em,style=sameline,font={\normalfont}]
    \item [Bit 0 (\textbf{TE})] indicates if the \ac{FIC} should stay in the \textit{WAIT} phase until the trigger is detected.
    \item [Bit 1 (\textbf{XT})] decides the trigger's source: either the external trigger input (if set), or the internal trigger from the DUT (if unset).
    \item [Bit 2 (\textbf{R}) ] specifies if the user design should be reset by the \ac{FIC} at the beginning of the \textit{WAIT} phase.
    \item [Bit 7 (\textbf{U}) ] specifies that the current configuration shall not be activated. This can be used to retrieve
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                    the state of the Fault Detect signals without interrupting an active \textit{FAULT2} pattern.
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\end{description}
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Then, the 16 bits of the design ID is transmitted to allow the \ac{FIC} to
check the sent configuration for compatibility with the hardware configuration.
Its value is determined at instrumentation time and stored in the \ac{FIJI} Settings to be available during communication.
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An 8-bit CRC at the end protects the message against bit flips.
The polynomial used is 0xE0 with an initialization value of 0xFF.
The data for the CRC algorithm is input and output as big-endian.

\begin{figure}
    \centering
    \input{content/protocol_host_to_fic}
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    \caption{Host to \ac{FIC} communication message format}
      \label{fig:h2f}
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\end{figure}