spriteflyer_voter_rtl.vhd 2.47 KB
Newer Older
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
--------------------------------------------------------------------------------
-- Fault InJection Instrumenter (FIJI)
-- https://embsys.technikum-wien.at/projects/vecs/fiji
--
-- Copyright (C) 2017 Christian Fibich <fibich@technikum-wien.at>
-- Copyright (C) 2017 Stefan Tauner <tauner@technikum-wien.at>
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable
-- law or agreed to in writing, software, hardware and materials
-- distributed under this License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either expressed or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- See the LICENSE file for more details.
--
-- Description:
--  TMR_VGA VGA voter
--------------------------------------------------------------------------------


25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
library ieee;
    use ieee.std_logic_1164.all;

entity spriteflyer_voter is
    generic (
        G_WIDTH : natural
    );
    port (
        s_en_i   : in std_logic;
        s_data_i : in std_logic_vector(3*G_WIDTH-1 downto 0);
        s_data_o : out std_logic_vector(G_WIDTH-1 downto 0);
        s_err_o  : out std_logic
    );
end entity spriteflyer_voter;

architecture rtl of spriteflyer_voter is

    signal s_error_internal : std_logic_vector(G_WIDTH-1 downto 0);

begin

    generate_majority_voter : for i in 0 to G_WIDTH-1 generate
    begin
        s_data_o(i) <= s_data_i(i) when s_en_i = '0' else
                      ((s_data_i(i)        and s_data_i(i+G_WIDTH))  or
                       (s_data_i(i)         and s_data_i(i+G_WIDTH*2)) or
                       (s_data_i(i+G_WIDTH) and s_data_i(i+G_WIDTH*2)));

        s_error_internal(i) <= ((s_data_i(i)         xor s_data_i(i+G_WIDTH))   or
                                (s_data_i(i)         xor s_data_i(i+G_WIDTH*2)) or
                                (s_data_i(i+G_WIDTH) xor s_data_i(i+G_WIDTH*2)));
    end generate;

    p_error_signal : process (s_en_i, s_error_internal)
        variable v_err : std_logic;
    begin
        v_err := '0';
        l_error_signal : for i in 0 to G_WIDTH-1 loop
            v_err := v_err or s_error_internal(i);
        end loop l_error_signal;
        s_err_o <= s_en_i and v_err;
    end process p_error_signal;

end rtl;