spriteflyer_clkgen_zybo.vhd 1.84 KB
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--------------------------------------------------------------------------------
-- Fault InJection Instrumenter (FIJI)
-- https://embsys.technikum-wien.at/projects/vecs/fiji
--
-- Copyright (C) 2017 Christian Fibich <fibich@technikum-wien.at>
-- Copyright (C) 2017 Stefan Tauner <tauner@technikum-wien.at>
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable
-- law or agreed to in writing, software, hardware and materials
-- distributed under this License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either expressed or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- See the LICENSE file for more details.
--
-- Description:
--  TMR_VGA zybo PLL architecture file
--------------------------------------------------------------------------------


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library ieee;
    use ieee.numeric_std.all;

architecture zybo of spriteflyer_clkgen is
    
    signal s_ce_count : unsigned (2 downto 0);
    signal s_reset_n  : std_logic;

begin
    s_clk_o     <= s_clk_i;
    s_reset_n   <= not s_reset_x_i;
    s_reset_n_o <= s_reset_n;


    -- 25 MHz clken from input clock clk
    p_clken : process (s_clk_i, s_reset_n)
     begin
        if s_reset_n = '0' then
            s_ce25_o   <= '0';
            s_ce_count <= "000";
        elsif s_clk_i'event and s_clk_i = '1' then
            s_ce25_o   <= '0';
            s_ce_count <= s_ce_count + 1;
            if s_ce_count = "100" then
                s_ce25_o <= '1';
                s_ce_count <= "000";
            end if;
        end if;
    end process p_clken;

end zybo;