tinyvga.v 5.61 KB
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// ------------------------------------------------------------------------------
//  Fault InJection Instrumenter (FIJI)
//  https://embsys.technikum-wien.at/projects/vecs/fiji
// 
//  Copyright (C) 2017 Christian Fibich <fibich@technikum-wien.at>
//  Copyright (C) 2017 Stefan Tauner <tauner@technikum-wien.at>
// 
//  Copyright and related rights are licensed under the Solderpad Hardware
//  License, Version 0.51 (the "License"); you may not use this file except
//  in compliance with the License. You may obtain a copy of the License at
//  http://solderpad.org/licenses/SHL-0.51. Unless required by applicable
//  law or agreed to in writing, software, hardware and materials
//  distributed under this License is distributed on an "AS IS" BASIS,
//  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either expressed or
//  implied. See the License for the specific language governing
//  permissions and limitations under the License.
// 
//  See the LICENSE file for more details.
// 
//  Description:
//   HX8K Demo Toplevel Module
// ------------------------------------------------------------------------------

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`default_nettype none

module tinyvga (input  osc,
                output reg [3:0] red,
                output reg [3:0] green,
                output reg [3:0] blue,
                output reg [7:0] led,
                output reg hsync,
                output reg vsync);

    wire clk36m;
    wire reset;
    wire locked;
    reg  [2:0]  reset_sync;

    // VGA
    wire blank;
    wire [10:0] column_next;
    wire [9:0]  line_next;
    reg  [9:0]  column;
    reg  [9:0]  line;

    // Image mover
    reg  [5:0]  sinetab [127:0];
    reg  [6:0]  memcol;
    reg  [5:0]  memcol_off;
    reg  [5:0]  memln;
    reg  [5:0]  memln_off;
    reg  [7:0]  frame_cnt;
    wire [7:0]  frame_cnt_next;

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    // Logo
    reg  [6:0]  logocol;
    reg  [5:0]  logoln;

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    ////////////////////////////////////////////////////////////////////

    pll pll_i(.clock_in(osc),.clock_out(clk36m),.locked(locked));

    always @(posedge clk36m or negedge locked) begin
        if (!locked)
            reset_sync <= "111";
        else
            reset_sync <= {reset_sync[1:0],1'b0};
    end

    assign reset = reset_sync[2];

    ////////////////////////////////////////////////////////////////////

    assign column_next    = {1'b0, column} + 11'b1;
    assign line_next      = line + 10'b1;
    assign blank          = ((column_next > 800) || (line_next > 600));
    assign frame_cnt_next = frame_cnt + 1;

    always @(posedge clk36m) begin
        if (reset) begin
            column       <= 10'b0;
            line         <= 10'b0;
            hsync        <= 1'b0;
            vsync        <= 1'b0;
            memcol       <= 7'h0;
            memln        <= 6'h0;
            frame_cnt    <= 8'b0;
            led          <= 8'b0;
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            logocol      <= 8'b0;
            logoln       <= 7'b0;
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        end else begin
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            column  <= column_next[9:0];
            memcol  <= column[7:1] + memcol_off;
            memln   <= line[6:1] + memln_off;
            led     <= frame_cnt;
            logocol <= column[9:2] - 8'd36;
            logoln  <= line[7:2] - 7'd43;
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            if (column == 823)
                hsync <= 1'b1;
            else if (column == 895)
                hsync <= 1'b0;

            if (column_next[10]) begin
                line      <= line_next;

                if (line == 601)
                    vsync <= 1'b1;
                else if (line == 603)
                    vsync <= 1'b0;
                else if (line == 624) begin
                    line <= 10'b0;
                    frame_cnt <= frame_cnt_next;
                end
            end
        end
    end

    ////////////////////////////////////////////////////////////////////

    wire [6:0] sinetab_addr_a;
    wire [6:0] sinetab_addr_b;

    assign sinetab_addr_a = frame_cnt[6:0];
    assign sinetab_addr_b = frame_cnt[6:0]+6'd32;

    always @(posedge clk36m) begin
        if (reset) begin
            memln_off  <= 0;
            memcol_off <= 0;
        end else begin
            memln_off  <= sinetab[sinetab_addr_a];
            memcol_off <= sinetab[sinetab_addr_b];
        end
    end

    initial
        $readmemh("sinetab.mem",sinetab);

    ////////////////////////////////////////////////////////////////////

    reg [11:0] imem [8191:0];
    reg [11:0] memline;

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    reg [1:0] logo[8191:0];
    reg [1:0] logoline;
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    initial begin
        $readmemh("color.mem",imem);
        $readmemb("logo.mem",logo);
    end
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    always @(posedge clk36m) begin
        if (reset) begin
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            red      <= 4'b0;
            green    <= 4'b0;
            blue     <= 4'b0;
            memline  <= 12'b0;
            logoline <= 2'b0;
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        end else begin
            memline = imem[{memln,memcol}];
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            logoline = logo[{logoln,logocol}];
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            if (blank) begin
                red   <= 4'b0;
                green <= 4'b0;
                blue  <= 4'b0;
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            end else if (logoline > 2'b0 && line > 171 && line < 428 && column > 143 && column < 656) begin
                if (logoline == 2'b01) begin
                    red   <= {2'b0,memline[11:10]};
                    green <= {2'b0,memline[7:6]};
                    blue  <= {2'b0,memline[3:2]};
                end else begin
                    red   <= {logoline[0],memln_off[4:2]};
                    green <= {logoline[0],memln_off[4:2]};
                    blue  <= {logoline[0],memln_off[4:2]};
                end
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            end else begin
                red   <= memline[11:8];
                green <= memline[7:4];
                blue  <= memline[3:0];
            end
        end
    end

endmodule