pll_hx8k.v 1.77 KB
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// ------------------------------------------------------------------------------
//  Fault InJection Instrumenter (FIJI)
//  https://embsys.technikum-wien.at/projects/vecs/fiji
// 
//  Copyright (C) 2017 Christian Fibich <fibich@technikum-wien.at>
//  Copyright (C) 2017 Stefan Tauner <tauner@technikum-wien.at>
// 
//  Copyright and related rights are licensed under the Solderpad Hardware
//  License, Version 0.51 (the "License"); you may not use this file except
//  in compliance with the License. You may obtain a copy of the License at
//  http://solderpad.org/licenses/SHL-0.51. Unless required by applicable
//  law or agreed to in writing, software, hardware and materials
//  distributed under this License is distributed on an "AS IS" BASIS,
//  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either expressed or
//  implied. See the License for the specific language governing
//  permissions and limitations under the License.
// 
//  See the LICENSE file for more details.
// 
//  Description:
//   HX8K Demo PLL module generated by icepll
// ------------------------------------------------------------------------------

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/**
 * PLL configuration
 *
 * This Verilog module was generated automatically
 * using the icepll tool from the IceStorm project.
 * Use at your own risk.
 *
 * Given input frequency:        12.000 MHz
 * Requested output frequency:   36.000 MHz
 * Achieved output frequency:    36.000 MHz
 */

module pll(
	input  clock_in,
	output clock_out,
	output locked
	);

SB_PLL40_CORE #(
		.FEEDBACK_PATH("SIMPLE"),
		.DIVR(4'b0000),		// DIVR =  0
		.DIVF(7'b0101111),	// DIVF = 47
		.DIVQ(3'b100),		// DIVQ =  4
		.FILTER_RANGE(3'b001)	// FILTER_RANGE = 1
	) uut (
		.LOCK(locked),
		.RESETB(1'b1),
		.BYPASS(1'b0),
		.REFERENCECLK(clock_in),
		.PLLOUTCORE(clock_out)
		);

endmodule