05-synthesis.tex

\section{Implementation}

\subsection{Synthesis}
\label{sec:Synthesis}

After instrumentation, the instrumented netlist and the HDL description
of the fault injection logic have to be combined into one netlist for 
FPGA implementation. To that end, the following steps have to be taken:

\begin{enumerate}
    \item Create a project in the synthesis tool
    \item Add an implementation for the exact same target technology and
          device for which the original netlist was generated
    \item Add as source files:
    \begin{itemize}
        \item the modified \ac{DUT} netlist (\texttt{*\_instrumented.vqm})
        \item the generated VHDL file containing the configuration package (\texttt{*\_config\_pkg.vhd})
        \item the generated VHDL file containing the wrapper entity (\texttt{*\_wrapper.vhd})
        \item the VHDL sources of the fault injection logic (located in \texttt{\$FIJI\_ROOT/hw/rtl/})
    \end{itemize}
    \item Set the name of the wrapper entity as top-level entity (\texttt{wrap} of type \texttt{fiji\_top}).
    \item Add any \textit{synthesis} constraint files existing from the
          original synthesis project and adapt their paths to HDL modules in the
          \ac{DUT} as necessary (one layer of hierarchy will be added as the
          module is instantiated by the wrapper VHDL entity).
    \item Optionally, add the \textit{synthesis} constraints file generated
          by the \textit{\ac{FIJI} Instrumentation} tool. The constraints in
          this file attempt to enforce the cross-hierarchy optimization
          level between the fault injection logic and the generated \ac{DUT}
          netlist (See \ref{sec:preventing_optimizations}).
    \item Optionally, add any additional \textit{synthesis} constraints.
\end{enumerate}

\subsubsection{Preventing Optimizations}
\label{sec:preventing_optimizations}

It may be desirable to prevent cross-hierarchy optimization between the
fault injection logic and the modified \ac{DUT} netlist, e.g. to prevent further
modification of the already verified \ac{DUT} netlist or to preserve existing
constraints for parts of the original netlist.

Synopsys' \textit{Synplify Pro} offers the possibility to define \textit{Compile
Points} which correspond to modules in a HDL design \cite{synpmanual}. At the start of the
compilation process, Synplify checks if the source for each compile point
has changed since the last compilation. Only compile points whose source
has changed are resynthesized.
Thus, to prevent cross-boundary optimization and resynthesis of the \ac{DUT} netlist,
a compile point has to be defined for the instantiated \ac{DUT}.

To do this via the Synplify GUI, the following steps have to be executed:
\begin{enumerate}
    \item Create the project and implementation, and add all source files
          including the \ac{DUT} netlist
    \item Synplify needs to parse the design's hierarchy. Thus, perform
          \textit{Compile only} \keystroke{F7}.
    \item Afterwards, open the SCOPE constraints editor (e.g., be double-clicking
          on the \texttt{*.fdc} file where the constraints shall be added)
    \item In the \textit{Compile Points} tab, add a new compile point:
        \begin{enumerate}
            \item Double-click in the \textit{View} field in an empty row
            \item Select the DUT's top-level entity name in the drop-down
                  menu
            \item Set the \textit{Type} field to \textit{locked}.
        \end{enumerate}
\end{enumerate}

To do this using a \textit{synthesis} constraints file (\texttt{fdc}), add
the following constraint:
\begin{verbatim}
define_compile_point  {v:[<library>].<DUT toplevel entity name>} -type {locked}
\end{verbatim}

The \textit{library} string point to the library where the \ac{DUT} can be
found. It can be omitted if the \ac{DUT} is compiled into the \texttt{work} library.


\subsubsection{Constraints Export}

When the \textit{Optimizations} setting in the \textit{\ac{FIJI} Setup} tool
(see Section~\ref{sec:setup}) is set to \texttt{OPTIMIZATION\_OFF} or \texttt{FIX\_PLACEMENT},
\textit{\ac{FIJI} Instrument} generates a \texttt{*\_constraints.synplify.fdc} file for Synplify.

This file contains the necessary constraints to prevent cross-boundary optimization
between the fault injection logic and the logic in the \ac{DUT} netlist. In order to
use the constraints contained in this file, it needs to be added as a source
file to the Synplify project and activated in the ``Implementation Options``.

\subsection{Place and Route}
\label{sec:place_and_route}

The synthesis process described in Section~\ref{sec:Synthesis} results in
one or more netlist files implementing the instrumented \ac{DUT} and the fault
injection logic. These netlist files must now be placed and routed using
an FPGA vendor's P\&R tool.

For this purpose, the following steps may be necessary across a variety
of P\&R tools:

\begin{enumerate}
    \item Create a project in the P\&R tool.
          It may be necessary to specify the family, device, and package
          of the target once again.
    \item Add the netlist files from the synthesis process as source
          files to this project.
    \item Add the original pin constraints to the P\&R project. The names
          of external pins in the original design are not changed by the
          instrumentation process.
    \item Add new location constraints for the external pins introduced
          by the instrumentation process (\textit{RX}, \textit{TX},
          and, if present, external reset and trigger pins)
    \item Add any other \textit{P\&R} constraints such as timing constraints
          existing from the original project. It may be necessary for some 
          constraints to adapt the target path as one layer of hierarchy
          is added by the wrapper entity.
\end{enumerate}

\subsubsection{Fixing Physical Placement Manually}
\label{sec:fixing_physical_placement}

It may be desired to fix the physical location of the \ac{DUT} netlist, so
that the mapping to specific logic elements is unchanged even if the
fault injection logic is modified. This can be useful in the following
cases:
\begin{itemize}
    \item The baud rate for communication with the host is changed
    \item The timer length or \ac{LFSR} configuration (Length, polynomial, seed) is changed
    \item External trigger or reset support is added or removed
    \item \textit{The \texttt{g\_implement\_fault\_injection} generic in the
          wrapper is set to \texttt{false}}

          This replaces the entire fault injection logic with wires
          connecting directly the generated \textit{original} net outputs 
          and the \textit{modified} net inputs.
          Thus, the netlist used in fault injection testing can be used
          unmodified in the final bitstream.
\end{itemize}

This can be achieved using location constraints in the FPGA vendors'
P\&R tools, although names and exact definition processes vary across
different tools.

\paragraph{Altera Quartus}\hfill\\

To fix the physical placement of a (sub)hierarchy in Altera Quartus,
perform the following steps in the Quartus GUI:
\begin{enumerate}
    \item After project setup, perform at least an \textit{Analysis~\&~Synthesis}
          run, so Quartus can parse the design hierarchy
    \item In the \textit{Project Navigator}, select the \textit{Hierarchy Browser}
          tab
    \item Unfold the top level entity in the tree view
    \item Right-click on the top-level entity of the \ac{DUT} netlist (\texttt{i\_DUT})
    \item In the context menu, navigate to \textit{LogicLock Region} and
          select \textit{Create new LogicLock Region}
    \item A new \textit{floating} region for placement is created.
          This means that neither the size nor the origin of the partition
          is specified yet.
          This \textit{floating} region can be converted to a \textit{locked}
          region with specified size and origin in two ways:
          \begin{itemize}
               \item When an upper bound for the size is known, the height
                     and width (in CLBs) can be entered manually. The
                     \textit{Size} can then be set to \textit{Fixed} and
                     the \textit{State} to \textit{Locked} in the
                     \textit{LogicLock Regions Window}. The fitter will
                     issue an error message if the selected region is too
                     small or does not contain enough special resources (e.g., BRAMs
                     or \textit{DSP Blocks}).
               \item After a complete compilation run, Quartus has determined
                     the area requirement for the current fit, and set the height,
                     width, and origin for the \textit{floating} region automatically.
                     To fix these values now set the \textit{Size} to \textit{Fixed} and
                     the \textit{State} to \textit{Locked} in the
                     \textit{LogicLock Regions Window}.
          \end{itemize}
\end{enumerate}

\paragraph{Xilinx Vivado}\hfill\\

To fix the physical placement of a (sub)hierarchy in Xilinx Vivado,
perform the following steps in the Vivado GUI:
\begin{enumerate}
    \item Set up a \textit{Post-Synthesis Project} with the
          synthesized netlist of the entire design (output of the second
          synthesis process) as a source file.
    \item Open the \textit{Synthesized Design} perspective.
    \item In the \textit{Netlist} tab, right-click on the top-level entity
          of the \ac{DUT} netlist (\texttt{i\_DUT}).
    \item In the context menu, navigate to \textit{Floorplanning} and
          select \textit{New Pblock}. A Pblock is Xilinx Vivado's equivalent
          to Altera's \textit{LogicLock Region}.
    \item In the menu bar, navigate to \textit{Tools $\rightarrow$ Floorplanning}
          and execute \textit{Place Pblocks}. This will use the information
          from the netlist to generate appropriately sized FPGA regions
          for all Pblocks. To reserve area for future expansions, a 
          target utilization can be set for each Pblock.
    \item Once the Pblock has been placed, it can be reviewed in the 
          \textit{Netlist} tab of the \textit{Synthesized Design} perspective:
          \begin{enumerate}
            \item Select the top-level entity of the Pblock.
            \item In the \textit{General} tab of the \textit{Cell Properties} window,
                  the name of the Pblock to which this entity is assigned is shown.
            \item Right-click on the name of that Pblock and select \textit{Pblock Properties}
                  in the context menu.
            \item The \textit{Pblock Properties} windows is opened.
                  Here, in the \textit{Statistics} tab, the block utilization
                  can be viewed. In the \textit{Rectangles} tab, the position
                  and size of the Pblock can be changed manually.
          \end{enumerate}
    \item Optionally, the location of the Pblock can also be changed in the device's floorplan.
\end{enumerate}

\subsubsection{Constraints Export}

When the \textit{Optimizations} setting in the \textit{\ac{FIJI} Setup} tool
(see Section~\ref{sec:setup}) is set to \texttt{FIX\_PLACEMENT},
\textit{\ac{FIJI} Instrument} generates template constraints files for
the selected P\&R tool (\texttt{*.qsf} for Altera Quartus, \texttt{*.xdc} for Xilinx Vivado).

These files contain the necessary directives to set up a physical partition for the
\ac{DUT} entity. They can either be imported into the P\&R tool directly or copied 
manually to a central constraints file.