05-synthesis.tex 11.4 KB
Newer Older
 1 2 \section{Implementation}  Christian Fibich committed May 04, 2018 3 4 \subsection{Synthesis} \label{sec:Synthesis}  5   Christian Fibich committed May 04, 2018 6 7 After instrumentation, the instrumented netlist and the HDL description of the fault injection logic have to be combined into one netlist for  Stefan Tauner committed May 04, 2018 8 FPGA implementation. To that end, the following steps have to be taken:  Christian Fibich committed May 04, 2018 9 10 11 12 13 14 15  \begin{enumerate} \item Create a project in the synthesis tool \item Add an implementation for the exact same target technology and device for which the original netlist was generated \item Add as source files: \begin{itemize}  Stefan Tauner committed May 04, 2018 16 17 18 19  \item the modified \ac{DUT} netlist (\texttt{*\_instrumented.vqm}) \item the generated VHDL file containing the configuration package (\texttt{*\_config\_pkg.vhd}) \item the generated VHDL file containing the wrapper entity (\texttt{*\_wrapper.vhd}) \item the VHDL sources of the fault injection logic (located in \texttt{\$FIJI\_ROOT/hw/rtl/})  Christian Fibich committed May 04, 2018 20  \end{itemize}  Stefan Tauner committed May 04, 2018 21  \item Set the name of the wrapper entity as top-level entity (\texttt{wrap} of type \texttt{fiji\_top}).  Christian Fibich committed May 04, 2018 22  \item Add any \textit{synthesis} constraint files existing from the  Stefan Tauner committed May 04, 2018 23  original synthesis project and adapt their paths to HDL modules in the  Stefan Tauner committed May 04, 2018 24  \ac{DUT} as necessary (one layer of hierarchy will be added as the  Stefan Tauner committed May 04, 2018 25  module is instantiated by the wrapper VHDL entity).  Christian Fibich committed May 04, 2018 26  \item Optionally, add the \textit{synthesis} constraints file generated  Christian Fibich committed May 04, 2018 27  by the \textit{\ac{FIJI} Instrumentation} tool. The constraints in  Christian Fibich committed May 04, 2018 28  this file attempt to enforce the cross-hierarchy optimization  Stefan Tauner committed May 04, 2018 29  level between the fault injection logic and the generated \ac{DUT}  Stefan Tauner committed May 04, 2018 30 31  netlist (See \ref{sec:preventing_optimizations}). \item Optionally, add any additional \textit{synthesis} constraints.  Christian Fibich committed May 04, 2018 32 33 34 35 36 37 \end{enumerate} \subsubsection{Preventing Optimizations} \label{sec:preventing_optimizations} It may be desirable to prevent cross-hierarchy optimization between the  Stefan Tauner committed May 04, 2018 38 39 fault injection logic and the modified \ac{DUT} netlist, e.g. to prevent further modification of the already verified \ac{DUT} netlist or to preserve existing  Christian Fibich committed May 04, 2018 40 41 42 43 44 45 46 constraints for parts of the original netlist. Synopsys' \textit{Synplify Pro} offers the possibility to define \textit{Compile Points} which correspond to modules in a HDL design \cite{synpmanual}. At the start of the compilation process, Synplify checks if the source for each compile point has changed since the last compilation. Only compile points whose source has changed are resynthesized.  Stefan Tauner committed May 04, 2018 47 48 Thus, to prevent cross-boundary optimization and resynthesis of the \ac{DUT} netlist, a compile point has to be defined for the instantiated \ac{DUT}.  Christian Fibich committed May 04, 2018 49   Stefan Tauner committed May 04, 2018 50 To do this via the Synplify GUI, the following steps have to be executed:  Christian Fibich committed May 04, 2018 51 52 \begin{enumerate} \item Create the project and implementation, and add all source files  Stefan Tauner committed May 04, 2018 53  including the \ac{DUT} netlist  Christian Fibich committed May 04, 2018 54  \item Synplify needs to parse the design's hierarchy. Thus, perform  Christian Fibich committed May 04, 2018 55  \textit{Compile only} \keystroke{F7}.  Christian Fibich committed May 04, 2018 56  \item Afterwards, open the SCOPE constraints editor (e.g., be double-clicking  Stefan Tauner committed May 04, 2018 57  on the \texttt{*.fdc} file where the constraints shall be added)  Christian Fibich committed May 04, 2018 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72  \item In the \textit{Compile Points} tab, add a new compile point: \begin{enumerate} \item Double-click in the \textit{View} field in an empty row \item Select the DUT's top-level entity name in the drop-down menu \item Set the \textit{Type} field to \textit{locked}. \end{enumerate} \end{enumerate} To do this using a \textit{synthesis} constraints file (\texttt{fdc}), add the following constraint: \begin{verbatim} define_compile_point {v:[].} -type {locked} \end{verbatim}  Stefan Tauner committed May 04, 2018 73 74 The \textit{library} string point to the library where the \ac{DUT} can be found. It can be omitted if the \ac{DUT} is compiled into the \texttt{work} library.  Christian Fibich committed May 04, 2018 75   Christian Fibich committed May 04, 2018 76 77 78 79 80  \subsubsection{Constraints Export} When the \textit{Optimizations} setting in the \textit{\ac{FIJI} Setup} tool (see Section~\ref{sec:setup}) is set to \texttt{OPTIMIZATION\_OFF} or \texttt{FIX\_PLACEMENT},  Stefan Tauner committed May 04, 2018 81 \textit{\ac{FIJI} Instrument} generates a \texttt{*\_constraints.synplify.fdc} file for Synplify.  Christian Fibich committed May 04, 2018 82 83  This file contains the necessary constraints to prevent cross-boundary optimization  Stefan Tauner committed May 04, 2018 84 between the fault injection logic and the logic in the \ac{DUT} netlist. In order to  Christian Fibich committed May 04, 2018 85 86 87 use the constraints contained in this file, it needs to be added as a source file to the Synplify project and activated in the Implementation Options.  Christian Fibich committed May 04, 2018 88 89 90 91 \subsection{Place and Route} \label{sec:place_and_route} The synthesis process described in Section~\ref{sec:Synthesis} results in  Stefan Tauner committed May 04, 2018 92 one or more netlist files implementing the instrumented \ac{DUT} and the fault  Christian Fibich committed May 04, 2018 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 injection logic. These netlist files must now be placed and routed using an FPGA vendor's P\&R tool. For this purpose, the following steps may be necessary across a variety of P\&R tools: \begin{enumerate} \item Create a project in the P\&R tool. It may be necessary to specify the family, device, and package of the target once again. \item Add the netlist files from the synthesis process as source files to this project. \item Add the original pin constraints to the P\&R project. The names of external pins in the original design are not changed by the instrumentation process. \item Add new location constraints for the external pins introduced by the instrumentation process (\textit{RX}, \textit{TX}, and, if present, external reset and trigger pins) \item Add any other \textit{P\&R} constraints such as timing constraints existing from the original project. It may be necessary for some constraints to adapt the target path as one layer of hierarchy is added by the wrapper entity. \end{enumerate}  Christian Fibich committed May 04, 2018 117 \subsubsection{Fixing Physical Placement Manually}  Christian Fibich committed May 04, 2018 118 119 \label{sec:fixing_physical_placement}  Stefan Tauner committed May 04, 2018 120 It may be desired to fix the physical location of the \ac{DUT} netlist, so  Christian Fibich committed May 04, 2018 121 122 123 124 125 that the mapping to specific logic elements is unchanged even if the fault injection logic is modified. This can be useful in the following cases: \begin{itemize} \item The baud rate for communication with the host is changed  Stefan Tauner committed May 04, 2018 126  \item The timer length or \ac{LFSR} configuration (Length, polynomial, seed) is changed  Christian Fibich committed May 04, 2018 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141  \item External trigger or reset support is added or removed \item \textit{The \texttt{g\_implement\_fault\_injection} generic in the wrapper is set to \texttt{false}} This replaces the entire fault injection logic with wires connecting directly the generated \textit{original} net outputs and the \textit{modified} net inputs. Thus, the netlist used in fault injection testing can be used unmodified in the final bitstream. \end{itemize} This can be achieved using location constraints in the FPGA vendors' P\&R tools, although names and exact definition processes vary across different tools.  Stefan Tauner committed May 04, 2018 142 \paragraph{Altera Quartus}\hfill\\  Christian Fibich committed May 04, 2018 143   Christian Fibich committed May 04, 2018 144 145 146 147 148 149 150 151 To fix the physical placement of a (sub)hierarchy in Altera Quartus, perform the following steps in the Quartus GUI: \begin{enumerate} \item After project setup, perform at least an \textit{Analysis~\&~Synthesis} run, so Quartus can parse the design hierarchy \item In the \textit{Project Navigator}, select the \textit{Hierarchy Browser} tab \item Unfold the top level entity in the tree view  Stefan Tauner committed May 04, 2018 152  \item Right-click on the top-level entity of the \ac{DUT} netlist (\texttt{i\_DUT})  Christian Fibich committed May 04, 2018 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167  \item In the context menu, navigate to \textit{LogicLock Region} and select \textit{Create new LogicLock Region} \item A new \textit{floating} region for placement is created. This means that neither the size nor the origin of the partition is specified yet. This \textit{floating} region can be converted to a \textit{locked} region with specified size and origin in two ways: \begin{itemize} \item When an upper bound for the size is known, the height and width (in CLBs) can be entered manually. The \textit{Size} can then be set to \textit{Fixed} and the \textit{State} to \textit{Locked} in the \textit{LogicLock Regions Window}. The fitter will issue an error message if the selected region is too small or does not contain enough special resources (e.g., BRAMs  Stefan Tauner committed May 04, 2018 168  or \textit{DSP Blocks}).  Christian Fibich committed May 04, 2018 169 170 171 172 173 174 175 176  \item After a complete compilation run, Quartus has determined the area requirement for the current fit, and set the height, width, and origin for the \textit{floating} region automatically. To fix these values now set the \textit{Size} to \textit{Fixed} and the \textit{State} to \textit{Locked} in the \textit{LogicLock Regions Window}. \end{itemize} \end{enumerate}  Christian Fibich committed May 04, 2018 177   Stefan Tauner committed May 04, 2018 178 \paragraph{Xilinx Vivado}\hfill\\  Christian Fibich committed May 04, 2018 179 180 181 182 183 184 185 186 187  To fix the physical placement of a (sub)hierarchy in Xilinx Vivado, perform the following steps in the Vivado GUI: \begin{enumerate} \item Set up a \textit{Post-Synthesis Project} with the synthesized netlist of the entire design (output of the second synthesis process) as a source file. \item Open the \textit{Synthesized Design} perspective. \item In the \textit{Netlist} tab, right-click on the top-level entity  Stefan Tauner committed May 04, 2018 188  of the \ac{DUT} netlist (\texttt{i\_DUT}).  Christian Fibich committed May 04, 2018 189 190  \item In the context menu, navigate to \textit{Floorplanning} and select \textit{New Pblock}. A Pblock is Xilinx Vivado's equivalent  Stefan Tauner committed May 04, 2018 191  to Altera's \textit{LogicLock Region}.  Christian Fibich committed May 04, 2018 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209  \item In the menu bar, navigate to \textit{Tools$\rightarrow\$ Floorplanning} and execute \textit{Place Pblocks}. This will use the information from the netlist to generate appropriately sized FPGA regions for all Pblocks. To reserve area for future expansions, a target utilization can be set for each Pblock. \item Once the Pblock has been placed, it can be reviewed in the \textit{Netlist} tab of the \textit{Synthesized Design} perspective: \begin{enumerate} \item Select the top-level entity of the Pblock. \item In the \textit{General} tab of the \textit{Cell Properties} window, the name of the Pblock to which this entity is assigned is shown. \item Right-click on the name of that Pblock and select \textit{Pblock Properties} in the context menu. \item The \textit{Pblock Properties} windows is opened. Here, in the \textit{Statistics} tab, the block utilization can be viewed. In the \textit{Rectangles} tab, the position and size of the Pblock can be changed manually. \end{enumerate}  Stefan Tauner committed May 04, 2018 210  \item Optionally, the location of the Pblock can also be changed in the device's floorplan.  Christian Fibich committed May 04, 2018 211 212 \end{enumerate}  Christian Fibich committed May 04, 2018 213 214 215 216 217 \subsubsection{Constraints Export} When the \textit{Optimizations} setting in the \textit{\ac{FIJI} Setup} tool (see Section~\ref{sec:setup}) is set to \texttt{FIX\_PLACEMENT}, \textit{\ac{FIJI} Instrument} generates template constraints files for  Stefan Tauner committed May 04, 2018 218 the selected P\&R tool (\texttt{*.qsf} for Altera Quartus, \texttt{*.xdc} for Xilinx Vivado).  Christian Fibich committed May 04, 2018 219 220  These files contain the necessary directives to set up a physical partition for the  Stefan Tauner committed May 04, 2018 221 \ac{DUT} entity. They can either be imported into the P\&R tool directly or copied  Christian Fibich committed May 04, 2018 222 manually to a central constraints file.