01-intro.tex 2.96 KB
 Christian Fibich committed May 04, 2018 1 \section{Introduction}  Christian Fibich committed May 04, 2018 2   Christian Fibich committed May 04, 2018 3 The \ac{FIJI} suite provides a tool flow for  Christian Fibich committed May 04, 2018 4 5 performing fault injection tests on chip designs in an FPGA-based environment. In contrast to fault injection tests by modification of the RTL source,  Christian Fibich committed May 04, 2018 6 \ac{FIJI} targets the already synthesized design at the FPGA primitive level (e.g.,  Christian Fibich committed May 04, 2018 7 LUTs, Flip-Flops, and the nets connecting them). Compared to fault injection  Christian Fibich committed May 04, 2018 8 carried out with the help of partial reconfiguration, \ac{FIJI} is relatively  Christian Fibich committed May 04, 2018 9 10 11 technology-independent as no knowledge about the bitstream format and the mapping to configuration frames within the FPGA device is required.  Stefan Tauner committed May 04, 2018 12 13 An overview of the \ac{FIJI} tool flow is shown in Figure~\ref{fig:fijiflow} and explained below. Data and actions framed in red in the picture have to be supplied by the user.  Christian Fibich committed May 04, 2018 14   Stefan Tauner committed May 04, 2018 15 \ac{FIJI} works by instrumenting a given netlist of a \ac{DUT} with  Christian Fibich committed May 04, 2018 16 fault injection logic according to a predefined fault injection configuration.  Christian Fibich committed May 04, 2018 17 A parametrized \ac{FIC} hardware module is added outside  Christian Fibich committed May 04, 2018 18 of the original design. The generation of the fault injection configuration  Christian Fibich committed May 04, 2018 19 20 and the parametrization of the \ac{FIC} is aided by the graphical user interface provided by the \textit{\ac{FIJI} Setup} tool, but can also be performed manually  Christian Fibich committed May 04, 2018 21 22 23 or by a script, as this information is stored in text files in an INI-like format.  Christian Fibich committed May 04, 2018 24 Instrumentation is done by the \textit{\ac{FIJI} Instrument} tool. This tool  Christian Fibich committed May 04, 2018 25 26 27 28 29 30 modifies the original netlist, and generates wrapper and configuration packages in VHDL. The user is then required to perform synthesis and place~\&~route of the modified design and download the generated bitstream to the target hardware.  Christian Fibich committed May 04, 2018 31 32 Test execution is facilitated by the \textit{\ac{FIJI} Download} and \textit{\ac{FIJI} Download GUI} tools. These tools communicate with the \ac{FIC}  Christian Fibich committed May 04, 2018 33 34 35 36 37 over a standard (TTL-)serial interface, and instruct the fault injection logic which tests to perform. Both of these tools support the execution of manually specified tests, execution of test sequences, and randomly generated test sequences.  Christian Fibich committed May 04, 2018 38 39 40 41 42 43 44 \begin{figure}[ht] \centering \input{img/fiji_sequence} \caption{\ac{FIJI} Tool Flow} \label{fig:fijiflow} \end{figure}  Christian Fibich committed May 04, 2018 45 46 47 48 Figure \ref{fig:fijioverview} provides an overview of the components present in the host (PC) and the target hardware to facilitate fault injection tests.  Christian Fibich committed May 04, 2018 49 50 51 \begin{figure}[ht] \centering \includegraphics[width=0.85\linewidth]{img/Overview.pdf}  Christian Fibich committed May 04, 2018 52 \caption{\ac{FIJI} Overview}  Christian Fibich committed May 04, 2018 53 54 55 \label{fig:fijioverview} \end{figure}  Christian Fibich committed May 04, 2018 56 All \ac{FIJI} tools are written in Perl.  Christian Fibich committed May 04, 2018 57   Christian Fibich committed May 04, 2018 58 The following data is used as an input to \ac{FIJI}:  Christian Fibich committed May 04, 2018 59 60 61 62 \begin{itemize} \item The netlist to be subjected to fault injection. Only Verilog-based netlists are supported, such as Altera's  Christian Fibich committed May 04, 2018 63  \ac{VQM} format, and Xilinx's \ac{VM} format.  Christian Fibich committed May 04, 2018 64 65 66 67 68  \item Meta-information about the design (e.g., clock frequency) \item The desired fault injection configuration (which faults on which nets) \item The desired capabilities of the Fault Injection Controller (e.g., communication data rate, timer sizes) \end{itemize}