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\section{Introduction}
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The \ac{FIJI} suite provides a tool flow for
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performing fault injection tests on chip designs in an FPGA-based environment.
In contrast to fault injection tests by modification of the RTL source,
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\ac{FIJI} targets the already synthesized design at the FPGA primitive level (e.g.,
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LUTs, Flip-Flops, and the nets connecting them). Compared to fault injection
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carried out with the help of partial reconfiguration, \ac{FIJI} is relatively
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technology-independent as no knowledge about the bitstream format and
the mapping to configuration frames within the FPGA device is required.

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An overview of the \ac{FIJI} tool flow is shown in Figure~\ref{fig:fijiflow} and explained below.
Data and actions framed in red in the picture have to be supplied by the user.
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\ac{FIJI} works by instrumenting a given netlist of a \ac{DUT} with
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fault injection logic according to a predefined fault injection configuration.
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A parametrized \ac{FIC} hardware module is added outside
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of the original design. The generation of the fault injection configuration
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and the parametrization of the \ac{FIC} is aided by the graphical user interface
provided by the \textit{\ac{FIJI} Setup} tool, but can also be performed manually
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or by a script, as this information is stored in text files in an INI-like
format.

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Instrumentation is done by the \textit{\ac{FIJI} Instrument} tool. This tool
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modifies the original netlist, and generates wrapper and configuration
packages in VHDL.

The user is then required to perform synthesis and place~\&~route of the
modified design and download the generated bitstream to the target hardware.

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Test execution is facilitated by the \textit{\ac{FIJI} Download} and
\textit{\ac{FIJI} Download GUI} tools. These tools communicate with the \ac{FIC}
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over a standard (TTL-)serial interface, and instruct the fault injection
logic which tests to perform. Both of these tools support the execution of
manually specified tests, execution of test sequences, and randomly generated
test sequences.

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\begin{figure}[ht]
\centering
\input{img/fiji_sequence}
\caption{\ac{FIJI} Tool Flow}
\label{fig:fijiflow}
\end{figure}

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Figure \ref{fig:fijioverview} provides an overview of the components
present in the host (PC) and the target hardware to facilitate fault
injection tests.

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\begin{figure}[ht]
\centering
\includegraphics[width=0.85\linewidth]{img/Overview.pdf}
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\caption{\ac{FIJI} Overview}
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\label{fig:fijioverview}
\end{figure}

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All \ac{FIJI} tools are written in Perl.
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The following data is used as an input to \ac{FIJI}:
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\begin{itemize}
    \item The netlist to be subjected to fault injection.
          
          Only Verilog-based netlists are supported, such as Altera's
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          \ac{VQM} format, and Xilinx's \ac{VM}  format.
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    \item Meta-information about the design (e.g., clock frequency)
    \item The desired fault injection configuration (which faults on which nets)
    \item The desired capabilities of the Fault Injection Controller (e.g., communication data rate, timer sizes)
\end{itemize}