tinyvga_fiji.fdc 1.35 KB
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###==== BEGIN Header

# Synopsys, Inc. constraint file
# /home/fibich/git/vecs/fiji/fiji_public/docs/demos/tinyvga/impl/instrumented/synp/tinyvga_fiji.fdc
# Written on Wed Sep 13 15:39:05 2017
# by Synplify Pro, J-2014.09-SP2 FDC Constraint Editor

# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
# These sections are generated from SCOPE spreadsheet tabs.

###==== END Header

###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
###==== END Collections

###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
create_clock  -name {s_fiji_clk} {n:s_fiji_clk} -period {28}

###==== END Clocks

###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
###==== END "Generated Clocks"

###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
###==== END Inputs/Outputs

###==== BEGIN Registers - (Populated from tab in SCOPE, do not edit)
###==== END Registers

###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
###==== END "Delay Paths"

###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
###==== END Attributes

###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
###==== END "I/O Standards"

###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
###==== END "Compile Points"